Resistive memory device including column decoder and method of performing a bidirectional driving operation and providing appropriate biasing with respect to bit lines
| Title: | Resistive memory device including column decoder and method of performing a bidirectional driving operation and providing appropriate biasing with respect to bit lines |
|---|---|
| Patent Number: | 9,589,632 |
| Publication Date: | March 07, 2017 |
| Appl. No: | 14/820197 |
| Application Filed: | August 06, 2015 |
| Abstract: | A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch. |
| Inventors: | Park, Hyun-Kook (Anyang-si, KR); Yoon, Chi-Weon (Seoul, KR); Lee, Yeong-Taek (Seoul, KR) |
| Assignees: | Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR) |
| Claim: | 1. A resistive memory device comprising: a memory cell array comprising memory cells connected to a plurality of signal lines; and a column decoder comprising a first switch unit comprising at least two pairs of switches arranged in correspondence to each of the plurality of signal lines and a second switch unit comprising a pair of switches arranged in correspondence to the at least two pairs of switches of the first switch unit, wherein: the first switch unit comprises a first pair of switches connected to a first signal line, wherein the first pair of switches comprises a first switch and a second switch that are of the same type, and the second switch unit comprises a second pair of switches comprising a third switch and a fourth switch that are connected to the first pair of switches, and a selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch. |
| Claim: | 2. The resistive memory device of claim 1 , wherein the plurality of signal lines are word lines or bit lines. |
| Claim: | 3. The resistive memory device of claim 1 , wherein the first switch comprises a first NMOS transistor and the second switch comprises a second NMOS transistor. |
| Claim: | 4. The resistive memory device of claim 3 , wherein: the third switch comprises a third NMOS transistor connected between a first line transferring the selection voltage and an end of the first NMOS transistor, and the fourth switch comprises a fourth NMOS transistor connected between a second line transferring the inhibit voltage and the end of the first NMOS transistor. |
| Claim: | 5. The resistive memory device of claim 4 , wherein: the first NMOS transistor is connected to a node between the third NMOS transistor and the fourth NMOS transistor, and the second NMOS transistor is connected to the second line. |
| Claim: | 6. The resistive memory device of claim 4 , wherein the first NMOS transistor is switched in response to a first control signal, and the second NMOS transistor is switched in response to a first complementary control signal. |
| Claim: | 7. The resistive memory device of claim 6 , wherein the third NMOS transistor is switched in response to a second control signal, and the fourth NMOS transistor is switched in response to a second complementary control signal. |
| Claim: | 8. The resistive memory device of claim 1 , wherein when the first signal line is selected, the selection voltage is provided to the first signal line by using an exclusive path comprising the third switch and the first switch. |
| Claim: | 9. The resistive memory device of claim 1 , wherein when the first signal line is not selected, the inhibit voltage is provided to the first signal line via the second switch, depending on a switching state of the first pair of switches. |
| Claim: | 10. The resistive memory device of claim 1 , wherein when the first signal line is not selected, the inhibit voltage is provided to the first signal line via the fourth switch and the first switch, depending on a switching state of the first pair of switches. |
| Claim: | 11. The resistive memory device of claim 1 , wherein: the column decoder further comprises a first line transferring the selection voltage, a second line transferring the inhibit voltage, and a third line arranged as a voltage transfer path, the first switch is connected between the first signal line and the third line, the second switch is connected between the first signal line and the second line, the third switch is connected between the first line and the third line, and the fourth switch is connected between the second line and the third line. |
| Claim: | 12. The resistive memory device of claim 1 , wherein: the first switch unit further comprises pairs of switches arranged in correspondence to each of second through nth signal lines (n is an integer that is equal to or greater than 2), and the second pair of switches of the second switch unit are connected commonly to first through nth pairs of switches of the first switch unit. |
| Claim: | 13. The resistive memory device of claim 12 , wherein: each of the first through nth pairs of switches of the first switch unit comprises the first switch and the second switch that are of the same type, and with respect to pairs of switches not being selected of the first switch unit, some pairs of switches transfer the inhibit voltage via the first switch, and others of the pairs of switches transfer the inhibit voltage via the second switch. |
| Claim: | 14. A resistive memory device comprising: a memory cell array comprising memory cells connected to a plurality of signal lines; a column decoder comprising a first switch unit comprising switches that are arranged in correspondence to each of the plurality of signal lines in order to drive the plurality of signal lines, and a second switch unit comprising switches adjusting a voltage transfer path in order to bi-directionally drive the memory cells; and a write/read circuit performing write and read operations with respect to the memory cells via the column decoder, wherein the second switch unit further comprises a biasing switch unit controlling an inhibit voltage to be provided to at least one of the plurality of signal lines via an additional voltage transfer path, regardless of the bidirectional driving with respect to the plurality of signal lines. |
| Claim: | 15. The resistive memory device of claim 14 , wherein the first switch unit comprises: a first pair of switches having a CMOS structure and connected to a first signal line, and a first NMOS transistor of the first pair of switches is connected to a first line transferring one of a selection voltage and the inhibit voltage, and a first PMOS transistor of the first pair of switches is connected to a second line transferring the other of the selection voltage and the inhibit voltage. |
| Claim: | 16. The resistive memory device of claim 15 , wherein the second switch unit comprises a second pair of switches connected to the first line and a third pair of switches connected to the second line, as switches for bi-directionally driving the memory cells. |
| Claim: | 17. The resistive memory device of claim 16 , wherein: when the memory cells are driven according to a first polarity, the second pair of switches provide the selection voltage to the first line and the third pair of switches provide the inhibit voltage to the second line, and when the memory cells are driven according to a second polarity, the second pair of switches provide the inhibit voltage to the first line and the third pair of switches provide the selection voltage to the second line. |
| Claim: | 18. The resistive memory device of claim 15 , wherein the biasing switch unit comprises a first switch transferring the inhibit voltage to the first line and a second switch transferring the inhibit voltage to the second line. |
| Claim: | 19. The resistive memory device of claim 18 , wherein: the second switch unit comprises at least one pair of switches for bi-directionally driving the memory cells, in correspondence to a signal line group comprising the plurality of signal lines, and when the at least one pair of switches are activated as the signal line group is selected, the biasing switch unit is non-activated. |
| Claim: | 20. The resistive memory device of claim 18 , wherein: the second switch unit comprises at least one pair of switches for bi-directionally driving the memory cells, in correspondence to a signal line group comprising the plurality of signal lines, and when the at least one pair of switches are non-activated as the signal line group is not selected, the biasing switch unit is activated. |
| Patent References Cited: | 2012/0099367 April 2012 Azuma 2015/0109858 April 2015 Ha 2015/0243355 August 2015 Lee |
| Primary Examiner: | Yoha, Connie |
| Attorney, Agent or Firm: | Volentine & Whitt, PLLC |
| Accession Number: | edspgr.09589632 |
| Database: | USPTO Patent Grants |
| Language: | English |
|---|