Memory devices, memory systems, and related operating methods
| Title: | Memory devices, memory systems, and related operating methods |
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| Patent Number: | 9,406,359 |
| Publication Date: | August 02, 2016 |
| Appl. No: | 14/683186 |
| Application Filed: | April 10, 2015 |
| Abstract: | A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region. |
| Inventors: | Park, Hyun-Kook (Anyang-si, KR); Lee, Yeong-Taek (Seoul, KR); Byeon, Dae-Seok (Seongnam-si, KR); Yoon, Chi-Weon (Seoul, KR) |
| Assignees: | Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR) |
| Claim: | 1. A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array, the method comprising: dividing the memory cells according to cell regions; independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region; adjusting the plurality of read references based on read data from the cell regions; independently performing a read retry operation on memory cells of each cell region by using one of the adjusted plurality of read references; and determining whether a number of errors in read data returned by the read retry operations exceeds a critical value. |
| Claim: | 2. The method of claim 1 , further comprising: before the independently performing the read operations, performing a normal read operation on the memory cells by a normal read reference, wherein independently performing the read operations is part of a read retry operation performed in relation to the memory cells following the normal read operation. |
| Claim: | 3. The method of claim 2 , further comprising: determining a number of errors in read data returned by the normal read operation, wherein the read retry operation is performed only when the number of errors in the read data exceed a critical value. |
| Claim: | 4. The method of claim 1 , further comprising: storing read data returned by each of the independently performed read operations in a page buffer connected to the memory cells, wherein a number of the memory cells disposed in each of the cell regions is less than a size of the page buffer. |
| Claim: | 5. The method of claim 1 , wherein each one of the plurality of read references is differently determined with respect to respective second signal lines in the cell regions and crossing the first signal line. |
| Claim: | 6. The method of claim 5 , further comprising: setting a different read condition according to each one of the plurality of read references, wherein the setting of each read condition includes defining at least one of a voltage, a current, and a control signal applied to a read circuit connected to the second signal lines. |
| Claim: | 7. The method of claim 6 , wherein the voltage comprises at least one of a read voltage, a precharge voltage, a clamping voltage, and a reference voltage, the current comprises a reference current, and the control signal comprises at least one of a precharge enable signal and a sense amp enable signal. |
| Claim: | 8. The method of claim 1 , wherein the independently performing read operations includes simultaneously performing at least two read operations directed to memory cells disposed in at least two of the cell regions. |
| Claim: | 9. The method of claim 1 , wherein the independently performing read operations includes sequentially performing at least two read operations directed to memory cells disposed in at least two of the cell regions. |
| Claim: | 10. The method of claim 1 , wherein the first signal line is a word line, and the second signal lines are bit lines. |
| Claim: | 11. The method of claim 1 , wherein dividing the memory cells according to cell regions is performed according to error correction code (ECC) units. |
| Claim: | 12. The method of claim 1 , wherein dividing the memory cells according to cell regions comprises dividing the memory cells according to a physical address or a logical address. |
| Claim: | 13. A method of operating a memory system comprising a memory device including a plurality of memory cells disposed in a plurality of cell regions disposed in areas where first signal lines and second signal lines respectively cross in a memory cell array, and a memory controller, the method comprising: communicating a normal read command from the memory controller to the memory device directed to target memory cells selected from the plurality of memory cells; executing a normal read operation with respect to the target memory cells and storing normal read result data in a page buffer connected to the second signal lines; determining different read references respectively corresponding to each one of the plurality of cell regions; if a number of errors in the normal read result exceeds a critical value, communicating a read retry command together with information defining the different read references to the memory device and performing a read retry operation on the target memory cells; and adjusting the plurality of read references by analyzing the retry read result data. |
| Claim: | 14. The method of claim 13 , wherein the target memory cells are commonly connected to the same first signal line, and the determining of the different read references comprises respectively determining a read reference for each one of the second signal lines. |
| Claim: | 15. The method of claim 13 , further comprising: executing a read retry operation with respect to the target memory cells; storing retry read result data in the page buffer in response to the read retry operation, wherein the read retry operation comprises a plurality of read operations respectively directed to memory cells disposed in each one of the cell regions, and each one of the plurality of read operations is performed using one of the different read references. |
| Claim: | 16. A memory device comprising: a memory cell array including a plurality of memory cells disposed in areas where a plurality of first signal lines and a plurality of second signal lines cross each other; a write/read circuit configured to perform a write operation and a read operation on memory cells selected from the plurality of memory cells and including a page buffer that temporarily stores read data; a control logic configured to control a read operation on the selected memory cells by using a plurality of different read references respectively corresponding to a plurality of cell regions divided from the selected memory cells in a read retry section; and adjusting the plurality of read references by analyzing the retry read result data. |
| Claim: | 17. The memory device of claim 16 , wherein the selected memory cells are commonly connected to the same first signal line, and the plurality of read references are different for respective second signal lines respectively connected to the plurality of cell regions. |
| Patent References Cited: | 7865797 January 2011 Eguchi et al. 8154921 April 2012 Mokhlesi et al. 8189386 May 2012 Park et al. 8400814 March 2013 Tokiwa 8422291 April 2013 Kim et al. 8479083 July 2013 Chae et al. 2007/0036014 February 2007 Bolandrina 2008/0239851 October 2008 Lin 2008/0285351 November 2008 Shlick 2012/0057409 March 2012 Lee 2012/0268994 October 2012 Nagashima 2012/0314478 December 2012 Ha et al. 2013/0139036 May 2013 Lee 2013/0148435 June 2013 Matsunaga 2013/0159785 June 2013 Hashimoto 2013/0194883 August 2013 Lee 2013/0258778 October 2013 Oh 2014/0029355 January 2014 Choi et al. 2014/0043903 February 2014 Ok 2014/0075241 March 2014 Oh et al. 2014/0082459 March 2014 Li et al. 2016/0035417 February 2016 Park 07282537 October 1995 |
| Primary Examiner: | Alrobaie, Khamdan |
| Attorney, Agent or Firm: | Volentine & Whitt, PLLC |
| Accession Number: | edspgr.09406359 |
| Database: | USPTO Patent Grants |
| Language: | English |
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