Tunable error resilience computing
| Title: | Tunable error resilience computing |
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| Patent Number: | 8,832,707 |
| Publication Date: | September 09, 2014 |
| Appl. No: | 12/642908 |
| Application Filed: | December 21, 2009 |
| Abstract: | An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality if resources for completion of the task in accordance with a level of quality of service in a service level agreement. |
| Inventors: | Henderson, Daniel J. (Georgetown, TX, US); Kudva, Prabhakar N. (New York, NY, US); Nayar, Naresh (Rochester, MN, US); Sanda, Pia Naoko (Slingerlands, NY, US); Siegel, David William (Austin, TX, US); Van Oosten, James (Rochester, MN, US); Xenidis, James (Austin, TX, US) |
| Assignees: | International Business Machines Corporation (Armonk, NY, US) |
| Claim: | 1. A computer-implemented method for scheduling a plurality of resources in a runtime environment in accordance with a particular level of quality of service, comprising: configuring, by a processor of a computer, the runtime environment to include a plurality of components, each component containing a plurality of instructions; identifying, by the processor, a plurality of quality of service requirements for a service level agreement; identifying, by the processor, a plurality of resources within a computing system configured to perform the service level agreement; translating, by the processor, each of the plurality of quality of service requirements into a plurality of metrics for each of the plurality of resources in the runtime environment; storing, by the processor, the plurality of metrics in a metrics file in a storage device; translating, by the processor, the plurality of metrics into one attribute; associating a descriptor with a task in the service level agreement; storing, by the processor, the one attribute in the descriptor, the one attribute configured to inform the processor of a particular component in the runtime environment to be selected to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement; reading, by the processor, the one attribute that is stored in the descriptor; responsive to reading the one attribute, selecting, by the processor, the particular component of the plurality of components; and responsive to selecting the particular component, running, by the processor, the particular component to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement. |
| Claim: | 2. The computer-implemented method of claim 1 , further comprising: modifying the plurality of resources available to the runtime environment for running the task in response to a particular instruction of the particular component. |
| Claim: | 3. The computer implemented method of claim 1 , further comprising: invoking, by the processor, a plurality of patterns from a pattern library, wherein each of the plurality of patterns is a set of instructions to augment the runtime environment in order to meet the level of quality of service of the service level agreement indicated by the one attribute. |
| Claim: | 4. The computer-implemented method of claim 1 , further comprising: scheduling, by the processor, a resiliency operation on only a critical code segment of the task. |
| Claim: | 5. The computer implemented method of claim 1 , further comprising: embedding the descriptor in an application program that requested that the task be run. |
| Claim: | 6. A computer system for scheduling a plurality of resources in a runtime environment in accordance with a particular level of quality of service, the computer system comprising: a processor of a computer configuring the runtime environment to include a plurality of components, each component containing a plurality of instructions; the processor identifying a plurality of quality of service requirements for a service level agreement; the processor identifying a plurality of resources within a computing system configured to perform the service level agreement; the processor translating each of the plurality of quality of service requirements into a plurality of metrics for each of the plurality of resources in the runtime environment; the processor storing the plurality of metrics in a metrics file in a storage device; the processor translating the plurality of metrics into one attribute; the processor associating a descriptor with a task in the service level agreement; the processor storing the one attribute in the descriptor, the one attribute configured to inform the processor of a particular component in the runtime environment to be selected to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement; the processor reading the one attribute that is stored in the descriptor; responsive to reading the one attribute, the processor selecting the particular component of the plurality of components; and responsive to selecting the particular component, the processor running the particular component to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement. |
| Claim: | 7. The computer system of claim 6 , wherein the plurality of resources available to the runtime environment for running the task are modified in response to a particular instruction of the particular component. |
| Claim: | 8. The computer system of claim 6 , further comprising: the processor invoking a plurality of patterns from a pattern library, wherein each of the plurality of patterns is a set of instructions to augment the runtime environment in order to meet the level of quality of service of the service level agreement indicated by the one attribute. |
| Claim: | 9. The computer system of claim 6 , further comprising: the processor scheduling a resiliency operation on only a critical portion of the task. |
| Claim: | 10. The computer system of claim 6 , wherein the descriptor is embedded in an application program that requested that the task be run. |
| Claim: | 11. A computer program product for scheduling a plurality of resources in a runtime environment in accordance with a particular level of quality of service, the computer program product comprising: a non-transitory computer readable storage medium; a plurality of instructions stored in the computer readable storage medium, the plurality of instructions configured, by a processor of a computer, to perform actions comprising: configuring the runtime environment to include a plurality of components, each component containing a plurality of instructions; identifying a plurality of quality of service requirements for a service level agreement; identifying a plurality of resources within a computing system configured to perform the service level agreement; translating each of the plurality of quality of service requirements into a plurality of metrics for each of the plurality of resources in the runtime environment; storing the plurality of metrics in a metrics file in a storage device; translating the plurality of metrics into one attribute; associating a descriptor with a task in the service level agreement; storing the one attribute in the descriptor, the one attribute configured to inform the processor of a particular component in the runtime environment to be selected to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement; reading the one attribute that is stored in the descriptor; responsive to reading the one attribute, selecting, by the processor, the particular component of the plurality of components; and responsive to selecting the particular component, running, by the processor, the particular component to schedule the plurality of resources in order to complete the task in accordance with the particular level of quality of service in the service level agreement. |
| Claim: | 12. The computer program product of claim 11 , wherein the plurality of instructions further comprise: modifying the plurality of resources available to the runtime environment for running the task in response to a particular instruction of the particular component. |
| Claim: | 13. The computer program product of claim 11 , wherein the plurality of instructions further comprise: invoking a plurality of patterns from a pattern library, wherein each of the plurality of patterns is a set of instructions to augment the runtime environment in order to meet the level of quality of service of the service level agreement indicated by the one attribute. |
| Claim: | 14. The computer program product of claim 11 , wherein the plurality of instructions further comprise: scheduling a resiliency operation on only a critical code segment of the task. |
| Claim: | 15. The computer program product of claim 11 , wherein the plurality of instructions further comprise: embedding the descriptor in an application program that requested that the task be run. |
| Current U.S. Class: | 718/104 |
| Patent References Cited: | 7107285 September 2006 von Kaenel et al. 8037475 October 2011 Jackson 2004/0205206 October 2004 Naik et al. 2005/0071450 March 2005 Allen et al. 2005/0165925 July 2005 Dan et al. 2006/0288251 December 2006 Jackson 2007/0083588 April 2007 Keller et al. 2008/0034093 February 2008 Sutou 2008/0059214 March 2008 Vinberg et al. 2008/0120619 May 2008 Podila 2008/0148015 June 2008 Takamoto et al. 2008/0209033 August 2008 Ginter et al. 2008/0240150 October 2008 Dias et al. 2008/0320482 December 2008 Dawson et al. 2009/0043888 February 2009 Jackson 2009/0113434 April 2009 Podila 2009/0119673 May 2009 Bubba 2009/0313623 December 2009 Coskun et al. 2010/0153960 June 2010 Youn et al. |
| Other References: | Rosenblum, “Impact of Virtualization on Computer Architecture and Operating Systems”, ACM, ASPLOS'06, Oct. 2006, San Jose CA, pp. 1. cited by applicant Hankins et al., “Multiple Instruction Stream Processor”, Proceedings of the 33rd International Symposium on Computer Architecture (ISCA'06), 2006, IEEE, pp. 1-12. cited by applicant Wang et al., “Sequencer Virtualization”, ACM 2007, ICS'07, Jun. 2007, Seattle, WA, pp. 148-157. cited by applicant Briquet et al., “Reproducible Testing of Distributed Software with Middleware Virtualization and Simulation”, ACM 2008, PADTAD'08, Jul. 2008, Seattle WA, pp. 1-11. cited by applicant Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor”, IEEE Micro, vol. 24, No. 2, Mar.-Apr. 2004, USA, pp. 40-47. cited by applicant |
| Primary Examiner: | Swift, Charles |
| Attorney, Agent or Firm: | Yee & Associates, P.C. |
| Accession Number: | edspgr.08832707 |
| Database: | USPTO Patent Grants |
| Language: | English |
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