Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance
| Title: | Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance |
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| Patent Number: | 8,713,256 |
| Publication Date: | April 29, 2014 |
| Appl. No: | 13/336977 |
| Application Filed: | December 23, 2011 |
| Abstract: | Embodiments described herein vary an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor. |
| Inventors: | Sodhi, Inder M. (Folsom, CA, US); Damaraju, Satish K. (El Dorado Hills, CA, US); Jahagirdar, Sanjeev S. (Folsom, CA, US); Wells, Ryan D. (Folsom, CA, US) |
| Assignees: | Intel Corporation (Santa Clara, CA, US) |
| Claim: | 1. A method comprising: monitoring, with a power control unit, a last level data cache (LLC) to identify a reduced amount of the LLC being used by a processor to process data, wherein the LLC is shared between at least two cores of the processor; reducing an amount of the LLC available for use by the processor cores, based on a cache size control signal generated by the power control unit; reducing an amount of power supplied to the LLC and to the processor, based on the reduced amount of the LLC being used. |
| Claim: | 2. The method of claim 1 , further comprising: after reducing the amount of the LLC available and reducing the amount of power supplied to the LLC, monitoring the LLC to identify an increased amount of the LLC being used by the processor to process data and to identify smart cache expand heurestis; increasing an amount of the LLC available for use by the processor, based on the increased amount of the LLC being used; increasing an amount of power supplied to the LLC and to the processor, based on the increased amount of LLC being used. |
| Claim: | 3. The method of claim 2 , wherein the reduced amount and the increased amount of the LLC being used are related to an operating system and an application running on the processor; and wherein the reduced amount and the increased amount of the LLC available for use by the processor are based on metrics, heuristics or factors calculated based on an amount of the LLC being used. |
| Claim: | 4. The method of claim 2 , wherein the reduced amount and the increased amount of power supplied to the LLC and to the processor is based on the reduced amount and the increased amount of the LLC available for use by the processor. |
| Claim: | 5. The method of claim 2 , wherein reducing the amount of the LLC available comprises removing the processor's ability to access a portion of the LLC, based on the reduced amount of the LLC being used; and wherein reducing the amount of power supplied to the LLC comprises removing power from a part of the LLC having a size less than the size of the portion of the LLC. |
| Claim: | 6. The method of claim 5 , monitoring the LLC to identify the reduced amount and the increased amount of the LLC being used comprises periodically sniffing the cache; and wherein the portion of the LLC is selected to be in half megabyte increments. |
| Claim: | 7. The method of claim 1 , further comprising, prior to monitoring, the processor processing data comprising data stored in the LLC. |
| Claim: | 8. The method of claim 1 , further comprising: using a first power supply to increase and decrease the amount of power and a frequency supplied to the LLC and to the processor; and using a second power supply to supply a fixed amount of power and frequency to a Bus Interface Unit of the processor. |
| Claim: | 9. An apparatus comprising: a processor having an execution unit including a first core and a second core; a last level cache (LLC) shared by the first and second cores; a power control unit (PCU) to reduce an amount of power supplied to the LLC and to the processor, based on a reduced amount of the LLC being used by the processor and to monitor the LLC to identify the reduced amount of the LLC being used by the processor to process data; a finite state machine (FSM) the FSM to reduce an amount of the LLC available for use by the processor, based on a cache size control signal received from the PCU, the cache size control signal based on the reduced amount of the LLC being used. |
| Claim: | 10. The apparatus of claim 9 , further comprising: the PCU to, after reducing the amount of the LLC available and reducing the amount of power supplied to the LLC, monitor the LLC to identify an increased amount of the LLC being used by the processor to process data and to identify smart cache expand heurestis; the FSM to increase an amount of the LLC available for use by the processor, based on the increased amount of the LLC being used; the PCU to increase an amount of power supplied to the LLC and to the processor, based on the increased amount of the LLC being used. |
| Claim: | 11. The apparatus of claim 10 further comprising: the PCU to reduce an amount and increase an amount of power supplied to the LLC and to the processor, based on the reduced amount and the increased amount of the LLC available for use by the processor. |
| Claim: | 12. The apparatus of claim 9 further comprising: the PCU to periodically “sniffing” the cache to identify an amount of the LLC being used. |
| Claim: | 13. The apparatus of claim 9 further comprising: the FSM to remove the processor's ability to access a portion of the LLC, based on the reduced amount of the LLC being used; and the power control unit configured to remove power from a part of the LLC having a size less than the size of the portion of the LLC. |
| Claim: | 14. The apparatus of claim 9 further comprising: the processor to process data comprising data stored in the LLC. |
| Claim: | 15. The apparatus of claim 9 further comprising: the processor further comprising a Bus Interface Unit; wherein the power control unit to use a first power supply to increase and decrease the amount of power and a frequency supplied to the LLC and to the processor, and to use a second power supply to supply a fixed amount of power and frequency to the Bus Interface Unit. |
| Claim: | 16. A system comprising: a computing device having a processor and memory, the processor coupled to the memory to process data stored in the memory; the processor having an execution unit including a first core and a second core that share a last level cache (LLC); the execution unit coupled to a power control unit (PCU) and to a finite state machine (FSM), the FSM coupled to the power control unit; monitor code of the power control unit to monitor the cache to identify a reduced amount of cache being used by the processor to process data; the FSM to reduce an amount of cache available for use by the processor, based on a cache size control signal received from the power control unit, the cache size control signal based on the reduced amount of cache being used; the power control unit to reduce an amount of power supplied to the cache and to the processor, based on the reduced amount of cache being used. |
| Claim: | 17. The system of claim 16 , further comprising: the monitor code to, after reducing the amount of cache available and reducing the amount of power supplied to the cache, monitor the cache to identify an increased amount of cache being used by the processor to process data and to identify smart cache expand heurestis; the FSM to increase an amount of cache available for use by the processor, based on the increased amount of cache being used; the PCU to increase an amount of power supplied to the cache and to the processor, based on the increased amount of cache being used. |
| Claim: | 18. The system of claim 17 , further comprising: the PCU to reduce an amount and increase an amount of power supplied to the cache and to the processor, based on the reduced amount and the increased amount of cache available for use by the processor; and wherein the reduced amount and the increased amount of the cache available for use by the processor are based on metrics, heuristics or factors calculated based on an amount of cache being used. |
| Claim: | 19. The system of claim 16 , further comprising: the FSM to remove the processor's ability to access a portion of the cache, based on the reduced amount of cache being used; and the power control unit to remove power from a part of the cache having a size less than the size of the portion of the cache. |
| Current U.S. Class: | 711/122 |
| Patent References Cited: | 5831849 November 1998 Matsui 6043559 March 2000 Banerjee et al. 7664970 February 2010 Jahagirdar et al. 7880284 February 2011 Zelikson et al. 7917787 March 2011 Jahagirdar et al. 7953993 May 2011 Allarey et al. 2012/0173821 July 2012 Levenstein et al. |
| Primary Examiner: | Gu, Shawn X |
| Attorney, Agent or Firm: | Blakely, Sokoloff, Taylor & Zafman LLP |
| Accession Number: | edspgr.08713256 |
| Database: | USPTO Patent Grants |
| Language: | English |
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