Bibliographic Details
| Title: |
Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs |
| Patent Number: |
8,509,014 |
| Publication Date: |
August 13, 2013 |
| Appl. No: |
13/291620 |
| Application Filed: |
November 08, 2011 |
| Abstract: |
Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. By performing obvious repair during collection of the FBM data, testing and date storage resources can be saved. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. The compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited. |
| Inventors: |
Shvydun, Volodymyr (Los Altos, CA, US); Adham, Saman M. I. (Ontario, CA) |
| Assignees: |
Taiwan Semiconductor Manufacturing Company, Ltd. (TW) |
| Claim: |
1. A method of self-testing and self-repairing a random access memory (RAM), comprising: collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures; and wherein the RAM is divided into a number of segments; performing obvious repair of failed cells during the collecting of the failure data; analyzing the failure data in the two FBM data structure to determine repair methods; and repairing failed cells of the RAM by using the redundant rows and columns until either all failed cells are repaired or the redundant rows and columns are all used. |
| Claim: |
2. The method of claim 1 , wherein the obvious repair includes repairing failures causing a segment violation. |
| Claim: |
3. The method of claim 1 , wherein the obvious repair includes repairing failures causing column or row failures exceeding a respective column or row limit. |
| Claim: |
4. The method of claim 1 , wherein a first FBM data structure includes a column for row addresses and a plurality of columns for error flags, and wherein a second FBM data structure include a plurality of columns for column indexes corresponding to column addresses of failed cells. |
| Claim: |
5. The method of claim 4 , wherein each of the error flags is represented by a bit reflecting a pass or a fail. |
| Claim: |
6. The method of claim 1 , wherein the number of redundant columns is equal to the number of segments, and wherein each redundant column is used for column repair in an assigned segment. |
| Claim: |
7. The method of claim 1 , wherein the analyzing the failure data in the two FBM data structure to determine repair method further comprises: determining if there are sufficient redundant rows to repair rows with a segment violation. |
| Claim: |
8. The method of claim 1 , wherein the analyzing the failure data in the two FBM data structure to determine repair method further comprises: identifying segments with only one column fail for column repair. |
| Claim: |
9. The method of claim 1 , wherein the analyzing the failure data in the two FBM data structure to determine repair method further comprises: identifying a column with a first maximum number of fails; identifying a row with a second maximum number of fails; and comparing the first maximum number with the second maximum number to determine a larger number between the two maximum numbers; wherein the column or the row with the larger number is selected for repair. |
| Claim: |
10. The method of claim 1 , further comprising: removing the failure data stored in the two FBM data structure of the repaired columns and/or rows after repair. |
| Claim: |
11. The method of claim 1 , wherein the method is configurable to optimize repair efficiency for the RAM with an available area for integrated circuits of the self-testing and self-repair method. |
| Claim: |
12. The method of claim 4 , wherein each of the column indexes has 6 bits and the row address is represented by 9 bits. |
| Claim: |
13. The method of claim 1 , wherein the collecting failure data of the RAM is enabled by a built-in self-test (BIST) module, and wherein the analyzing and the repairing are performed by a built-in self-repair (BIST) module, and wherein the BIST and the BISR modules are integrated with the RAM. |
| Claim: |
14. The method of claim 1 , wherein the RAM is selected from a group consisting of static RAM (SRAM), dynamic RAM (DRAM), and flash memory. |
| Claim: |
15. The method of claim 1 , wherein the repairing is performed by registering an address of a repaired row or column and the address of the redundant row or column used for the repair, and wherein the FBM data structures are updated after the repairing is performed. |
| Claim: |
16. A method of self-testing and self-repairing a random access memory (RAM), comprising: collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures; and wherein the RAM is divided into a number of segments, wherein a first FBM data structure includes a column for row address and a plurality of columns for error flags, and wherein a second FBM data structure includes a plurality of columns for column indexes corresponding to column addresses of failed cells; performing obvious repair of failed cells during the collecting of the failure data; analyzing the failure data in the two FBM data structure to determine repair methods; and repairing failed cells of the RAM by using the redundant rows and columns until either all failed cells are repaired or the redundant rows and columns are all used. |
| Claim: |
17. A memory array with a built-in self-test (BIST) module and a built-in self-repair (BISR) module to repair a main memory of the memory array, comprising: the main memory; a first number of redundant rows for row repair of the main memory; a second number of redundant columns for column repair of the main memory, and wherein the main memory is evenly divided into the second number of segments and each redundant column is assigned for column repair in an assigned segment; the BIST module for testing the main memory; and the BISR module for repairing the main memory by using the redundant rows and redundant columns, wherein the BISR module performs obvious repair during testing of the main memory, and wherein the BISR instructs the BISR to stop testing untested portion of columns and rows repaired by obvious repairs, and wherein the BISR module performs other repairs based on failure bit maps (FBMs) generated from testing the entire main memory. |
| Claim: |
18. The memory array of claim 17 , wherein the BIST module includes an address generator, a data generator, and a test state controller, wherein a test pattern controlled by the test state controller is generated by the address generator and the data generator. |
| Claim: |
19. The memory array of claim 17 , wherein the BIST module includes a failure storage for storing failure data, a repair controller for analyzing the failure data to determine the repair method, and a repair register for registering the repaired rows and columns and the redundant columns and rows used, and wherein the failure storage includes the FBMs, and wherein the FBMs are updated after any repair is performed. |
| Claim: |
20. The memory array of claim 19 , wherein the failure storage further includes a failure data converter, wherein the failure data converter generates compressed failure data to be stored in a data structure for the FBM. |
| Current U.S. Class: |
365/200 |
| Patent References Cited: |
7187603 March 2007 Nagata et al. |
| Primary Examiner: |
Lam, David |
| Attorney, Agent or Firm: |
Lowe Hauptman Ham & Berner, LLP |
| Accession Number: |
edspgr.08509014 |
| Database: |
USPTO Patent Grants |
