Database creation method, database device and design data evaluation method
| Title: | Database creation method, database device and design data evaluation method |
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| Patent Number: | 8,195,697 |
| Publication Date: | June 05, 2012 |
| Appl. No: | 12/354594 |
| Application Filed: | January 15, 2009 |
| Abstract: | A database creation method relating to semiconductor ICs, the database registering function block cells constituting a design data of semiconductor IC and evaluation values corresponding to the function block cells such that the function block cells are associated with the evaluation values, for each of the semiconductor ICs, the creation method includes judging whether or not that function block cells constituting a design data of desired semiconductor IC include an unregistered function block cell which is not registered in the database, calculating an unregistered evaluation value corresponding to the unregistered function block cell when the function block cells constituting the design data of the desired semiconductor IC are judged to include the unregistered function block cell, and updating the database by registering the unregistered function block cell and the unregistered evaluation value such that the unregistered function block cell is associated with the unregistered evaluation value. |
| Inventors: | Maeda, Shimon (Tokyo, JP); Honda, Noriyuki (Kawasaki, JP) |
| Assignees: | Kabushiki Kaisha Toshiba (Tokyo, JP) |
| Claim: | 1. A computer-implemented creation method for database relating to a plurality of semiconductor integrated circuits, the database registering, for the semiconductor integrated circuits, a plurality of function block cells constituting a design data of the corresponding semiconductor integrated circuit and a plurality of evaluation values corresponding to the plurality of function block cells, such that the plurality of function block cells are associated with the plurality of evaluation values, the creation method comprising: judging, by a computer, whether a plurality of function block cells constituting design data of a desired semiconductor integrated circuit include an unregistered function block cell which is not registered in the database; calculating, by a computer, an unregistered evaluation value corresponding to the unregistered function block cell when the plurality of function block cells include the unregistered function block cell, the unregistered evaluation value including verification values of optical proximity effect correction (“OPC”) and process proximity correction (“PPC”) for a pattern corresponding to the unregistered function block cell, a critical area value for a pattern corresponding to the unregistered function block cell, and a probability that hot spot or failure portion causing reduction of yield is included in a pattern corresponding to the unregistered function block cell, wherein: the verification value of OPC or PPC corresponds to a difference between a cell shape after OPC or PPC and a reference cell shape, and the critical area value represents a size of an area in which a fatal defect occurs if particles are present; and updating, by a computer, the database by registering the unregistered function block cell and the unregistered evaluation value. |
| Claim: | 2. The creation method according to claim 1 , wherein the evaluation value includes the verification values, the critical area value, and the probability for each of process conditions. |
| Claim: | 3. The creation method according to claim 1 , wherein the plurality of function block cells are cells to perform a basic logical operation or cells to perform a predetermined logical function constructed by a plurality of basic logical operation. |
| Claim: | 4. The creation method according to claim 1 , wherein the calculating the unregistered evaluation value includes arranging a plurality of function block cells around the unregistered cell function block cells, and the unregistered evaluation value is calculated by considering the unregistered cell and the plurality of function block cells arranged around the unregistered cell as one unregistered cell. |
| Claim: | 5. The creation method according to claim 1 , wherein the design data includes a Graphic Database System (GDS) and a library-exchange format (LEF). |
| Claim: | 6. The creation method according to claim 5 , wherein the design data further includes a design-exchange format (DEF). |
| Claim: | 7. A non-transitory computer-readable storage medium storing a set of instructions which, when executed by a processor, cause the processor to perform a method comprising: accessing a database relating to a plurality of semiconductor integrated circuits, the database registering, for the semiconductor integrated circuits, a plurality of function block cells constituting design data of the corresponding semiconductor integrated circuit and a plurality of evaluation values corresponding to the plurality of function block cells, such that the plurality of function block cells are associated with the plurality of evaluation values; judging whether a plurality of function block cells constituting design data of a desired semiconductor integrated circuit include an unregistered function block cell which is not registered in the database; calculating an unregistered evaluation value corresponding to the unregistered function block cell when the plurality of function block cells include the unregistered function block cell, the unregistered evaluation value including verification values of optical proximity effect correction (“OPC”) and process proximity correction (“PPC”) for a pattern corresponding to the unregistered function block cell, a critical area value for a pattern corresponding to the unregistered function block cell, and a probability that hot spot or failure portion causing reduction of yield is included in a pattern corresponding to the unregistered function block cell, wherein: the verification value of OPC or PPC corresponds to a difference between a cell shape after OPC or PPC and a reference cell shape, and the critical area value represents a size of an area in which a fatal defect occurs if particles are present; and updating the database by registering the unregistered function block cell and the unregistered evaluation value. |
| Claim: | 8. The storage medium according to claim 7 , wherein calculating comprises arranging a plurality of function block cells around the unregistered cell function block cells, and calculating the unregistered evaluation value by considering the unregistered cell and the plurality of function block cells arranged around the unregistered cell as one unregistered cell. |
| Claim: | 9. A computer-implemented method for evaluating design data comprising: preparing, by a computer, a database relating to a plurality of semiconductor integrated circuits, the database registering, for the semiconductor integrated circuits, a plurality of function block cells constituting a design data of semiconductor integrated circuit and a plurality of evaluation values corresponding to the plurality of function block cells such that the plurality of function block cells are associated with the plurality of evaluation values, each of the evaluation values including verification values of optical proximity effect correction (“OPC”) and process proximity correction (“PPC”) for a pattern corresponding to the corresponding function block cell, a critical area value for a pattern corresponding to the corresponding function block cell, and a probability that hot spot or failure portion causing reduction of yield is included in a pattern corresponding to the corresponding function block cell, wherein: the verification value of OPC or PPC corresponds to a difference between a cell shape after OPC or PPC and a reference cell shape, and the critical area value represents a size of an area in which a fatal defect occurs if particles are present; extracting, by a computer, a plurality of evaluation values from the database, wherein the plurality of evaluation values are associated with a plurality of function block cells of a desired semiconductor integrated circuit in the plurality of semiconductor integrated circuits; and judging, by a computer, whether the design data of the desired semiconductor integrated circuit is acceptable or rejectable based on the extracted plurality of evaluation values. |
| Claim: | 10. The method according to claim 9 , wherein: the design data of the desired semiconductor integrated circuit is judged rejectable when an evaluation value not satisfying a criteria is found in the plurality of evaluation values associated with the plurality of function block cells constituting the design data of the desired semiconductor integrated circuit, and the method further comprises outputting information including the function block cell not satisfying the criteria to a storage unit when the design data of the desired semiconductor integrated circuit is judged rejectable. |
| Current U.S. Class: | 707/793 |
| Patent References Cited: | 6470489 October 2002 Chang et al. 6836877 December 2004 Dupenloup 7065724 June 2006 Caty et al. 7356788 April 2008 Chang et al. 7392503 June 2008 Wang 2001/0018758 August 2001 Tanaka et al. 4-7674 January 1992 6-268069 September 1994 07-311797 November 1995 2000-057188 February 2000 2003-243510 August 2003 2003-526110 September 2003 2004-54689 February 2004 2005-107883 April 2005 2007-12687 January 2007 2007-102420 April 2007 |
| Other References: | Notice of Reasons for Rejection, issued by Japanese Patent Office, dated Sep. 27, 2011, in a Japanese patent application No. 2008-007165, 4 pages. cited by other Notice of Reasons for Rejection mailed Feb. 3, 2012, from the Japanese Patent Office for counterpart Japanese Patent Application No. 2008-007165 (5 pages). cited by other |
| Assistant Examiner: | Tran, Anh Tai |
| Primary Examiner: | Vo, Tim T |
| Attorney, Agent or Firm: | Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P. |
| Accession Number: | edspgr.08195697 |
| Database: | USPTO Patent Grants |
| Language: | English |
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