Lead frame, lead frame fabrication, and semiconductor device
| Title: | Lead frame, lead frame fabrication, and semiconductor device |
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| Patent Number: | 8,125,062 |
| Publication Date: | February 28, 2012 |
| Appl. No: | 12/723894 |
| Application Filed: | March 15, 2010 |
| Abstract: | Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface. |
| Inventors: | Shoji, Masanobu (Tsuruoka, JP); Fujita, Toru (Tsuruoka, JP) |
| Assignees: | Seiko Epson Corporation (Tokyo, JP) |
| Claim: | 1. A method for fabricating a lead frame, the method comprising: forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface of the convex portion and a second portion that extends from the first portion and does not overlap the first surface; and bending the metal layer such that the second portion of the metal layer overlaps a second surface of the convex portion that intersects the first surface. |
| Claim: | 2. A method for fabricating a lead frame according to claim 1 , wherein the forming of the substrate includes forming the metal layer on a surface of a metal substrate, and forming the convex portion by wet etching the metal substrate using the metal layer as a mask. |
| Claim: | 3. A method for fabricating a lead frame according to claim 1 , wherein the forming of the substrate includes: coating a first resist film on a surface of a metal substrate; wet-etching the metal substrate with the first resist film as a mask; removing the first resist film after the wet-etching; coating a second resist film in a concave portion formed by the etching, after the removing of the first resist film; forming the metal layer on the metal substrate exposed through the second resist film, after the coating of the second resist film; and removing the second resist film, after the forming of the metal layer. |
| Claim: | 4. A method for fabricating a lead frame recited in claim 1 , wherein the forming of the substrate includes forming the substrate to have a plurality of the convex portions, wherein the plurality of the convex portions have the same shape and the same size. |
| Claim: | 5. A lead frame comprising: a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface of the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and wherein the second portion of the metal layer being bent in a manner to overlap a second surface of the convex portion that intersects the first surface. |
| Claim: | 6. A lead frame according to claim 5 , wherein an angle of intersection between the first surface and the second surface is an acute angle in a cross-sectional view. |
| Claim: | 7. A semiconductor device wherein comprising: a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface of the convex portion and a second portion that extends from the first portion and does not overlap the first surface; an IC element fixed to the substrate and having an electrode; a conductive member that connects the metal layer to the electrode of the IC element; and a resin that seals the IC element and the conductive member. |
| Current U.S. Class: | 257/666 |
| Patent References Cited: | 5847458 December 1998 Nakamura et al. 6528879 March 2003 Sakamoto et al. 6562660 May 2003 Sakamoto et al. 6700905 March 2004 Karasawa et al. 6946324 September 2005 McLellan et al. 7049177 May 2006 Fan et al. 7173336 February 2007 Sakamoto et al. 7276793 October 2007 Sakamoto et al. 2005/0202274 September 2005 Elschner et al. 2009/0032943 February 2009 Shoji et al. 2009/0034225 February 2009 Shoji et al. 2009/0243095 October 2009 Fujita et al. 2009/0302466 December 2009 Shoji et al. A-05-166985 July 1993 A-09-312355 December 1997 B2-3060020 April 2000 A-2001-024135 January 2001 A-2002-093847 March 2002 A-2002-280480 September 2002 B2-3609737 October 2004 B2-3780122 March 2006 A-2007-048981 February 2007 A-2007-281510 October 2007 B2-4032063 October 2007 A-2007-335464 December 2007 A-2009-055014 March 2009 A-2009-055015 March 2009 A-2009-246115 October 2009 A-2009-283746 December 2009 A-2009-302095 December 2009 |
| Primary Examiner: | Potter, Roy |
| Attorney, Agent or Firm: | Oliff & Berridge, PLC |
| Accession Number: | edspgr.08125062 |
| Database: | USPTO Patent Grants |
| Language: | English |
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