Method of fabricating high aspect ratio metal structures
| Title: | Method of fabricating high aspect ratio metal structures |
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| Patent Number: | 8,034,719 |
| Publication Date: | October 11, 2011 |
| Appl. No: | 11/311584 |
| Application Filed: | December 08, 2005 |
| Abstract: | To fabricate high aspect ratio metal structures, a two-layer structure is provided on a conductive layer. The two-layer structure includes a first layer adjacent the conductive layer and a second layer adjacent the first layer where the second layer is etchable by a Deep Reactive Ion Etching (DRIE) process. Using the DRIE process, at least one selected region of the second layer is completely etched away with the selected region being at least partially aligned with a region of the conductive layer such that the first layer is then exposed thereover. The first layer so-exposed is then removed to expose the region of the conductive layer thereunder. Metal is electroplated onto the exposed conductive layer and any remaining portions of the two-layer structure are then removed. |
| Inventors: | Jean, Daniel L. (Odenton, MD, US); Deeds, Michael (Port Tobacco, MD, US); Keeney, Allen (Upperco, MD, US) |
| Assignees: | The United States of America as represented by the Secretary of the Navy (Washington, DC, US) |
| Claim: | 1. A method of fabricating metal structures, comprising: providing a two-layer structure of selected thickness on at least one: conductive layer, said two-layer structure comprises a first layer adjacent said at least one conductive layer and a second layer adjacent said first layer; etching, using a Deep Reactive Ion Etching (DRIE) process, completely through at least one selected etchable region of said second layer with said at least one selected etchable region being at least partially aligned with a region of said at least one conductive layer; removing said first layer for exposing said region of said at least one conductive layer, wherein remaining portions of said two-layer structure and said region of said at least one conductive layer so-exposed define a mold, said mold comprises a base region; electroplating a metal onto said base region; and removing said remaining portions of said two-layer structure for forming a metal structure, wherein said at least one conductive layer comprises a plurality of conductive layers deposited in a pattern on a support substrate, wherein said first layer is comprised of silicon dioxide and said second layer is comprised of silicon, wherein said etching said at least one selected etchable region forms a trench in said silicon of said second layer, and wherein said electroplating includes filling said trench with said metal. |
| Claim: | 2. The method according to claim 1 , wherein said support substrate is an electrically non-conductive substrate. |
| Claim: | 3. The method according to claim 1 , wherein said removing is comprised of acid applied to said first layer so-exposed thereto. |
| Claim: | 4. The method according to claim 1 , wherein said at least one conductive layer and said metal electroplated onto said base region are both comprised of a same material. |
| Claim: | 5. The method according to claim 1 , wherein said at least one conductive layer and said metal electroplated onto said base region are each comprised of different metals. |
| Claim: | 6. The method according to claim 1 , wherein said removing said remaining portions of said two-layer structure is comprised of dissolving at least one of said first layer and said second layer associated with said remaining portions of said two-layer structure. |
| Claim: | 7. The method according to claim 1 , wherein said first layer is comprised of a material, which is not etchable by said DRIE process. |
| Claim: | 8. The method according to claim 1 , wherein said second layer is comprised of a material etchable by said DRIE process. |
| Claim: | 9. The method according to claim 1 , wherein said first layer is an exposed layer resulting from said etching. |
| Claim: | 10. The method according to claim 1 , wherein said first layer is exposed over said region of said at least one conductive layer. |
| Claim: | 11. The method according to claim 1 , further comprising sandwiching said at least one conductive layer between said two-layer structure and the support substrate. |
| Claim: | 12. The method according to claim 11 , wherein said support substrate is extended laterally beyond a periphery of said at least one conductive layer, and wherein said sandwiching includes said two-layer structure is bonded to said support substrate beyond said periphery. |
| Claim: | 13. The method according to claim 11 , further comprising removing at least one of a portion of said at least one conductive layer and a portion of said support substrate. |
| Claim: | 14. The method according to claim 1 , wherein said at least one conductive layer comprises a flat surface substantially adjacent said first layer. |
| Claim: | 15. The method according to claim 1 , wherein said at least one conductive layer comprises a plurality of conductive layers deposited in a pattern on a flat support substrate. |
| Claim: | 16. A method of fabricating metal structures, comprising: providing a two-layer structure of selected thickness on a conductive layer, said two-layer structure comprises a first layer adjacent said conductive layer and a second layer adjacent said first layer; etching, using a Deep Reactive Ion Etching (DRIE) process, completely through at least one selected etchable region of said second layer with said at least one selected etchable region being aligned with a region of said conductive layer, wherein said first layer is exposed over said region of said conductive layer; removing said first layer for exposing said region of said conductive layer, wherein remaining portions of said two-layer structure and said region of conductive layer so-exposed define a mold, said mold comprises a base region; electroplating a metal onto said base region; and removing said remaining portions of said two-layer structure for forming a metal structure, wherein said two-layer structure includes a first thickness, wherein said metal is electroplated so said metal structure comprises a second thickness at least as thick as the first thickness, wherein said first layer is comprised of silicon dioxide and said second layer is comprised of silicon, wherein said etching said at least one selected etchable region forms a trench in said silicon of said second layer, and wherein said electroplating includes filling said trench with said metal. |
| Claim: | 17. The method according to claim 16 , wherein said conductive layer is a metal backplane. |
| Claim: | 18. The method according to claim 16 , wherein said removing is comprised of an acid applied to said first layer. |
| Claim: | 19. The method according to claim 16 , wherein said conductive layer and said metal electroplated onto said base region are each comprised of different materials. |
| Claim: | 20. The method according to claim 16 , wherein said metal structure is a high aspect ratio metal structure. |
| Current U.S. Class: | 438/700 |
| Patent References Cited: | 6458615 October 2002 Fedder et al. 6673694 January 2004 Borenstein 6798200 September 2004 Fan 6875544 April 2005 Sweatt et al. 6946314 September 2005 Sawyer et al. 6960488 November 2005 Brosnihan et al. 2002/0176804 November 2002 Strand et al. 2003/0222648 December 2003 Fan 2004/0021005 February 2004 Stout et al. 2004/0196335 October 2004 Stout et al. 2005/0074676 April 2005 Watanabe et al. 2005/0153215 July 2005 Bornstein et al. 2005/0182307 August 2005 Currie et al. 2006/0055090 March 2006 Lee et al. |
| Other References: | Marc J. Madou, “Fundamentals of Microfabrication: The Science of Miniaturization,” CRC Press LLC, 2002, 325-377. cited by other |
| Assistant Examiner: | Garcia, Joannie A |
| Primary Examiner: | Smith, Matthew |
| Attorney, Agent or Firm: | Zimmerman, Fredric J. |
| Accession Number: | edspgr.08034719 |
| Database: | USPTO Patent Grants |
| Language: | English |
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