Selective transaction request processing at an interconnect during a lockout
| Title: | Selective transaction request processing at an interconnect during a lockout |
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| Patent Number: | 7,865,897 |
| Publication Date: | January 04, 2011 |
| Appl. No: | 11/347103 |
| Application Filed: | February 03, 2006 |
| Abstract: | A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences. |
| Inventors: | Eckermann, Benjamin C. (Tanunda, AU); Murdock, Brett W. (Round Rock, TX, US); Moyer, William C. (Dripping Springs, TX, US) |
| Assignees: | Freescale Semiconductor, Inc. (Austin, TX, US) |
| Claim: | 1. A method comprising: receiving, at an interconnect of an integrated circuit device, a first transaction request from a first requesting module of the integrated circuit device, the first transaction request including a request to utilize at least one resource accessible via the interconnect; accessing, at the interconnect, an entry of an interferences table associated with the first transaction request to determine potential interferences expected to occur as a result of a utilization of the at least one resource by the first requesting module, the entry including data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module; initiating processing of the first transaction request at the interconnect; and authorizing processing of a second transaction request from a second requesting module of the integrated circuit device during the processing of the first transaction request responsive to determining the second requesting module is represented in the first set. |
| Claim: | 2. The method of claim 1 , wherein the request to utilize at least one resource comprises a lockout request. |
| Claim: | 3. The method of claim 2 , wherein the entry of the interferences table is identified based on a transaction identifier associated with the first transaction request. |
| Claim: | 4. The method of claim 1 , wherein the entry comprises a plurality of bit positions, each bit position associated with a corresponding one of a plurality of requesting modules and having one of a first value or a second value, the first value indicating that the corresponding requesting module is expected to interfere with the utilization of the at least one resource by the first requesting module and the second value indicating the corresponding requesting module is not expected to interfere with the utilization of the at least one resource by the first requesting module. |
| Claim: | 5. The method of claim 4 , wherein the request to utilize at least one resource comprises a lockout request. |
| Claim: | 6. The method of claim 1 , wherein the entry further includes data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module. |
| Claim: | 7. The method of claim 6 , wherein: processing of the second transaction request is authorized when the first set includes the second requesting module; and processing of the second transaction request is denied when the second set includes the second requesting module. |
| Claim: | 8. The method of claim 1 , wherein the entry of the interferences table is identified based on a transaction identifier associated with the first transaction request. |
| Claim: | 9. The method of claim 1 , wherein: processing of the second transaction request is authorized when the second transaction request is not expected to interfere with the utilization of the at least one resource by the first requesting module; and processing of the second transaction request is denied when the second transaction request is expected to interfere with the utilization of the at least one resource by the first requesting module. |
| Claim: | 10. A method comprising: initiating, at a first time, processing of a first transaction request from a first requesting module of an integrated circuit device at an interconnect of the integrated circuit device; receiving, at a second time subsequent to the first time, a second transaction request from a second requesting module of the integrated circuit device; accessing, at the interconnect, an entry of a table based on transaction information associated with the first transaction request so as to determine whether the second transaction request is permitted to be processed at the interconnect concurrently with the first transaction request, the entry including data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module and data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module; initiating, at a third time subsequent to the second time, processing of the second transaction request at the interconnect when it is determined that the second transaction request is permitted to be processed concurrently with the first transaction request; and terminating, at a fourth time subsequent to the third time, the processing of the first transaction request. |
| Claim: | 11. The method of claim 10 , wherein: accessing the table based on the transaction identifier so as to determine whether the second transaction request is permitted to be processed includes determining whether the second requesting module is represented in the first set or represented in the second set. |
| Claim: | 12. The method of claim 11 , wherein: processing of the second transaction request is initiated at the interconnect when the second requesting module is represented in the first set; and processing of the second transaction request is denied at the interconnect when the second requesting module is represented in the second set. |
| Claim: | 13. The method of claim 11 , further comprising: denying processing of the second transaction request at the interconnect when it is determined that the second transaction request is not permitted to be processed concurrently with the first transaction request. |
| Claim: | 14. The method of claim 10 , further comprising: denying processing of the second transaction request at the interconnect when it is determined that the second transaction request is not permitted to be processed concurrently with the first transaction request. |
| Claim: | 15. The method of claim 14 , wherein: accessing the table based on the transaction identifier so as to determine whether the second transaction request is permitted to be processed includes determining whether the second requesting module is represented in the first set or represented in the second set. |
| Claim: | 16. The method of claim 10 , further comprising: receiving, at a fifth time subsequent to the first time and prior to the third time, a third transaction request from a third requesting module of the integrated circuit device; determining whether the third transaction request is permitted to be processed at the interconnect concurrently with the first transaction request based on the access of the table; and initiating, at a sixth time subsequent to the fifth time and prior to the fourth time, processing of the third transaction request at the interconnect when it is determined that the third transaction request is permitted to be processed concurrently with the first transaction request. |
| Claim: | 17. The method of claim 10 , wherein the first transaction request comprises a lockout request. |
| Claim: | 18. An integrated circuit device comprising: an inferences table; an interconnect operably coupled to a first requesting module, a second requesting module and a plurality of resources, the interconnect comprising: means for receiving a first transaction request from the first requesting module, the first transaction request including a request to utilize at least one resource of the plurality of resources; means for accessing an entry of the interferences table to determine potential interferences expected to occur as a result of a utilization of the at least one resource by the first requesting module, the entry comprising data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module and data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module; means for initiating processing of the first transaction request at the interconnect; and means for authorizing processing of a second transaction request from the second requesting module during the processing of the first transaction request responsive to determining the second requesting module is represented in the first set. |
| Claim: | 19. The integrated circuit device of claim 18 , wherein the entry comprises a plurality of bit positions, each bit position associated with a corresponding one of a plurality of requesting modules and having one of a first value or a second value, the first value indicating that the corresponding requesting module is expected to interfere with the utilization of the at least one resource by the first requesting module and the second value indicating the corresponding requesting module is not expected to interfere with the utilization of the at least one resource by the first requesting module. |
| Claim: | 20. The integrated circuit device of claim 18 , wherein: the interconnect authorizes processing of the second transaction request when the second transaction request is not expected to interfere with the utilization of the at least one resource by the first requesting module; and the interconnect denies processing of the second transaction request when the second transaction request is expected to interfere with the utilization of the at least one resource by the first requesting module. |
| Current U.S. Class: | 718/104 |
| Patent References Cited: | 5559979 September 1996 Shiga et al. 5913044 June 1999 Tran et al. 6098134 August 2000 Michels 6189007 February 2001 Boonie et al. 6323755 November 2001 Lee et al. 6493784 December 2002 Kamimura et al. 6745273 June 2004 Gehman 6775727 August 2004 Moyer 6801983 October 2004 Abe et al. 2002/0138677 September 2002 Brock et al. 2005/0097560 May 2005 Rolia et al. |
| Other References: | International Search Report and Written Opinion for correlating PCT Patent Application No. PCT/US06/62474 dated Jul. 8, 2008. cited by other Supplementary European Search Report mailed on Jul. 26, 2010 for Application EP 06 85 1333 (PCT/2006/062474), 5 pages. cited by other |
| Assistant Examiner: | Wai, Eric C |
| Primary Examiner: | Zhen, Li B |
| Accession Number: | edspgr.07865897 |
| Database: | USPTO Patent Grants |
| Language: | English |
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