FIFO sub-system with in-line correction
| Title: | FIFO sub-system with in-line correction |
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| Patent Number: | 7,574,541 |
| Publication Date: | August 11, 2009 |
| Appl. No: | 10/909999 |
| Application Filed: | August 03, 2004 |
| Abstract: | A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction. |
| Inventors: | Liav, Ori Ron (Fort Collins, CO, US); Ellis, Jackson Lloyd (Fort Collins, CO, US); Brocko, Kurt David (Fort Collins, CO, US) |
| Assignees: | LSI Logic Corporation (Milpitas, CA, US) |
| Claim: | 1. A first-in-first-out (FIFO) sub-system for a disk formatter for controlling movement of data in a data processing system, the first-in-first out (FIFO) sub-system comprising: a first FIFO unit, which has a first width, for receiving first data from and transferring second data to a first device using a first bursting channel having a first channel width, wherein the FIFO sub-system transfers the data according to a plurality of sector sizes; the first device coupled to a memory device, the first device for receiving said first data from said memory device and transferring said second data to said memory device; a second FIFO unit, which has a second width, for transferring said first data to and receiving said second data from a second device using a second bursting channel having a second channel width, wherein the second channel width is not a multiple of the first channel width and the first channel width is not a multiple of the second channel width, and wherein said second width is not a multiple of the first width and the first width is not a multiple of the second width; a third FIFO unit having the first width and interfacing between the first bursting channel and the first FIFO for transferring the data during a read operation; data width conversion means between the first FIFO unit and the second FIFO unit for converting said first data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and for converting said second data moving from the second FIFO unit to the first FIFO unit from the second width to the first width, wherein the data width conversion means comprises at least a first counter and a second counter, wherein the first counter and the second counter are sector counters, and wherein based on an indication from the sector counters, the data is adjusted to accommodate the plurality of sector sizes, by appending padding to the data as needed to convert said second data to the second FIFO unit during a write operation; and a third interface to a third channel having a third channel width for performing error correction, wherein the error correction during a read operation is performed as the data is moved from the second FIFO unit to a read converter, and wherein the error correction during a write operation is performed as the data is moved from the second FIFO unit to an external read/write device, wherein the error correction occurs as a part of the FIFO sub-system and within the disk formatter. |
| Claim: | 2. The FIFO sub-system of claim 1 , wherein the first bursting channel comprises a channel to a double data rate synchronous dynamic random access memory (DDR SDRAM) controller, the memory device is a double data rate synchronous dynamic random access memory (DDR SDRAM), the second device is the external read/write device, and the second bursting channel comprises a channel to a read/write channel device. |
| Claim: | 3. The FIFO sub-system of claim 1 , wherein the first channel width is 64-bits, the second channel width is 10-bits, and the third channel width is a multiple of the second width. |
| Claim: | 4. The FIFO sub-system of claim 3 , wherein the third channel width is 40-bits. |
| Claim: | 5. A method in a first-in-first-out (FIFO) sub-system for a disk formatter for controlling movement of data in a data processing system, the first-in-first out (FIFO) sub-system comprising: providing a first FIFO unit, which has a first width, for receiving first data from and transferring second data to a first device using a first bursting channel having a first channel width, wherein the FIFO sub-system transfers the data according to a plurality of sector sizes; the first device coupled to a memory device, the first device receiving said first data from said memory device and transferring said second data to said memory device; providing a second FIFO unit, which has a second width, for transferring said first data to and receiving said second data from a second device using a second bursting channel having a second channel width, wherein the second channel width is not a multiple of the first channel width and the first channel width is not a multiple of the second channel width, and wherein said second width is not a multiple of the first width and the first width is not a multiple of the second width; converting said first data moving from the first FIFO unit to the second FIFO unit from the first data width to the second data width, and converting said second data moving from the second FIFO unit to the first FIFO unit from the second data width to the first data width, wherein a first counter and a second counter are used in the conversion, wherein the first counter and the second counter are sector counters, and wherein, based on an indication by the sector counters, the data is adjusted to accommodate the plurality of sector sizes, wherein the data is adjusted by appending padding to the data as needed to convert said second data to the second FIFO unit during a write operation; and providing a third interface to a third channel having a third channel width for performing error correction, wherein the error correction during a read operation is performed as the data is moved from the second FIFO unit to a read converter, and wherein the error correction during a write operation is performed as the data is moved from the second FIFO unit to an external read/write device, wherein the error correction occurs as a part of the FIFO sub-system and within the disk formatter. |
| Claim: | 6. The method of claim 5 , wherein the first device is a double data rate synchronous dynamic random access memory (DDR SDRAM) controller, wherein the memory device is a double data rate synchronous dynamic random access memory (DDR SDRAM), and wherein the second device is the external read/write device. |
| Claim: | 7. The FIFO sub-system of claim 1 , wherein the first FIFO unit, the second FIFO unit, and the third FIFO unit are implemented using synchronous two-port RAM cells. |
| Claim: | 8. The FIFO sub-system of claim 1 , wherein data width conversion is performed in a middle section of the FIFO sub-system where no bursting requirement exists. |
| Current U.S. Class: | 710/66 |
| Patent References Cited: | 5220569 June 1993 Hartness 5359468 October 1994 Rhodes et al. 5590309 December 1996 Chencinski et al. 5761348 June 1998 Honma 5768546 June 1998 Kwon 6636949 October 2003 Barroso et al. 6961877 November 2005 Si et al. 7050461 May 2006 Abe et al. 2001/0036322 November 2001 Bloomfield et al. 2005/0033875 February 2005 Cheung et al. |
| Assistant Examiner: | Mamo, Elias |
| Primary Examiner: | Tsai, Henry W. H. |
| Attorney, Agent or Firm: | Yee & Associates, P.C. |
| Accession Number: | edspgr.07574541 |
| Database: | USPTO Patent Grants |
| Language: | English |
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