Stack type surface acoustic wave package, and method for manufacturing the same
| Title: | Stack type surface acoustic wave package, and method for manufacturing the same |
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| Patent Number: | 7,336,017 |
| Publication Date: | February 26, 2008 |
| Appl. No: | 11/217465 |
| Application Filed: | September 02, 2005 |
| Abstract: | A surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. |
| Inventors: | Lee, Seung Hee (Suwon, KR); Park, Doo Cheol (Suwon, KR); Park, Joo Hun (Suwon, KR); Lee, Young Jin (Yongin, KR); Park, Sang Wook (Suwon, KR); Kim, Nam Hyeong (Suwon, KR) |
| Assignees: | Samsung Electro-Mechanics Co., Ltd. (Kyungki-Do, KR) |
| Claim: | 1. A surface acoustic wave package, comprising: a first bare chip having a plurality of electrodes formed on a lower surface of said first bare chip; a second bare chip having a plurality of electrodes formed on an upper surface of said second bare chip and via-holes formed through said second bare chip, wherein the first bare chip is stacked on the second bare chip with the electrodes on the lower surface of the first bare chip facing the electrodes on the upper surface of said second bare chip; a connecting portion electrically connecting the electrodes of the first bare chip to corresponding ones of the electrodes of the second bare chip; and a sealing member provided on the first and second bare chips to form an air-tight space between the first and second bare chips; wherein the first and second bare chips are piezoelectric single crystal elements; the electrodes of each of the first and second bare chips comprise an input electrode, an output electrode, and IDT electrodes; and the IDT electrodes formed on the lower surface of the first bare chip are different in length, width, and gap between the IDT electrodes from the IDT electrodes formed on the upper surface of the second bare chip. |
| Claim: | 2. The package according to claim 1 , wherein the connecting portion includes: a conductive pad laid on the input and output electrodes of the first bare chip; a conductive pattern electrically connected to the via-holes of the second bare chip; and a metallic bonding agent interposed between said conductive pad and said conductive pattern. |
| Claim: | 3. The package according to claim 1 , wherein the connecting portion includes: a conductive pad laid on the input and output electrodes of the first bare chip; another conductive pad laid on the via-holes of the second bare chip; and a metallic bonding agent interposed between said conductive pad and said another conductive pad. |
| Claim: | 4. The package according to claim 3 , wherein the metallic bonding agent comprises an Au-based stud bump used for supersonic bonding. |
| Claim: | 5. The package according to claim 3 , wherein the metallic bonding agent comprises an AuSn-based solder bump used for thermal bonding. |
| Claim: | 6. The package according to claim 1 , wherein the sealing member comprises: a resin film laminated from an upper surface of the first bare chip to the upper surface of the second bare chip, said resin film surrounding side surfaces of the first bare chip; and a metal layer plated on the resin film to partially cover the upper surface of the second bare chip, and surround side and upper surfaces of the resin film. |
| Claim: | 7. The package according to claim 1 , wherein the sealing member comprises: a continuous metal dam interposed between the lower surface of the first bare chip and the upper surface of the second bare chip; and a metal layer extending from the metal dam to surround side and upper surfaces of the first bare chip. |
| Claim: | 8. The package according to claim 1 , wherein the sealing member is electrically connected to an inner ground terminal to prevent electromagnetic wave from being induced into the package from the outside. |
| Claim: | 9. The package according to claim 1 , wherein the input and output electrodes, and the IDT electrodes of the first bare chip face the input and output electrodes, and the IDT electrodes of the second bare chip, respectively. |
| Claim: | 10. The package according to claim 1 , further comprising a conductive pattern positioned on the upper surface of the second bare chip and electrically connecting upper ends of the via-holes to the input and output electrodes of the second bare chip. |
| Claim: | 11. The package according to claim 1 , further comprising a conductive pad positioned on and electrically connecting upper ends of the via-holes to the input and output electrodes of the second bare chip. |
| Claim: | 12. The package according to claim 1 , wherein the resin film comprises a thermosetting material. |
| Claim: | 13. The package according to claim 1 , wherein the resin film is selected from the group consisting of a polyimide based film and an epoxy-based film. |
| Current U.S. Class: | 310/313R |
| Patent References Cited: | 5699027 December 1997 Tsuji et al. 5747857 May 1998 Eda et al. 5818145 October 1998 Fukiharu 6329739 December 2001 Sawano 6339365 January 2002 Kawase et al. 6351194 February 2002 Takahashi et al. 6467139 October 2002 Tanaka 6628043 September 2003 Furukawa et al. 6803698 October 2004 Tabota 2004/0113215 June 2004 Shimada et al. 2007/0058003 March 2007 Aoki 07-111438 April 1995 09-181562 July 1997 2001176995 June 2001 |
| Other References: | Korean Intellectual Property Office, Office Action, mailed Aug. 25, 2006. cited by other |
| Primary Examiner: | Dougherty, Thomas M. |
| Attorney, Agent or Firm: | Lowe Hauptman Ham & Berner |
| Accession Number: | edspgr.07336017 |
| Database: | USPTO Patent Grants |
| Language: | English |
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