Method and system of bus master arbitration
| Title: | Method and system of bus master arbitration |
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| Patent Number: | 7,099,973 |
| Publication Date: | August 29, 2006 |
| Appl. No: | 10/402165 |
| Application Filed: | March 26, 2003 |
| Abstract: | A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150). |
| Inventors: | Moyer, William C. (Dripping Springs, TX, US); Fitzsimmons, Michael D. (Austin, TX, US); Murdock, Brett W. (Round Rock, TX, US) |
| Assignees: | Freescale Semiconductor, Inc. (Austin, TX, US) |
| Claim: | 1. A data processing system comprising: a plurality of bus masters; a first bus coupled to the plurality of bus masters; a first storage location to store a first bus master parking information for the first bus; a second storage location to store a second bus master parking information for the first bus; and a first arbiter comprising a first park context input, a plurality of request inputs coupled to the plurality of bus masters, wherein the first arbiter is coupled to the first storage location and to the second storage location, and each one of the plurality of request inputs is coupled to one of the plurality of bus masters, and the first park contest input is to receive a first state to indicate which of the first bus master parking information and the second bus master parking information the first arbiter is to access. |
| Claim: | 2. The system of claim 1 wherein the first bus master parking information comprises a writeable field to indicate which one of the plurality of bus masters is to be parked on the first bus. |
| Claim: | 3. The system of claim 1 further comprising: a second bus coupled to the plurality of bus masters; a third storage location to store a third bus master parking information for the second bus; a fourth storage location to store a fourth bus master parking information for the second bus; and a second arbiter comprising a second park context input, a plurality of request inputs coupled to the plurality of bus masters, wherein the second arbiter is coupled to the third storage location and to the fourth storage location, and each one of the request inputs is coupled to one of the plurality of bus masters, and the second park context input is to receive a second state to indicate which of the third bus master parking information and the fourth bus master parking information the second arbiter is to access. |
| Claim: | 4. The system of claim 3 , wherein the first arbiter and the second arbiter are part of a common arbiter. |
| Claim: | 5. The system of claim 1 further comprising a slave device coupled to the first park context input. |
| Claim: | 6. The system of claim 1 further comprising a slave device comprising an interrupt coupled to the first park context input. |
| Claim: | 7. The system of claim 1 , wherein the plurality of request inputs are bus request inputs coupled to a plurality of bus request outputs of a plurality of bus masters. |
| Claim: | 8. The system of claim 1 further comprising: a crossbar switch to couple the plurality of bus masters to the first bus. |
| Current U.S. Class: | 710/118 |
| Patent References Cited: | 5119486 June 1992 Albonesi 5193149 March 1993 Awiszio et al. 5297292 March 1994 Morimoto et al. 5345566 September 1994 Tanji et al. 5463740 October 1995 Taniai et al. 5572686 November 1996 Nunziata et al. 5581782 December 1996 Sarangdhar et al. 5596729 January 1997 Lester et al. 5752010 May 1998 Herbert 5826045 October 1998 Reams 5915102 June 1999 Chin 5923859 July 1999 Melo et al. 6073199 June 2000 Cohen et al. 6092219 July 2000 Porterfield 6157989 December 2000 Collins et al. 6163826 December 2000 Khan et al. 6269102 July 2001 Hayashi 6564280 May 2003 Walsh 6571306 May 2003 Smith 6823410 November 2004 Koike 6823411 November 2004 Hofmann et al. 2002/0099892 July 2002 Olarig 2003/0097505 May 2003 Kato 2003/0110231 June 2003 Roy 2003/0200375 October 2003 Kawaguchi 2000035943 February 2000 |
| Other References: | “PCI Arbiter Core,” Actel Corporation data sheet, 5172152-2/1.02, Jan. 2002, 4 pp. cited by other “MPC5200 User Manual,” Section 16 “XLB ARBITER,” Order No. MPC5200UM/D, Motorola, digital dna, Jul. 2003, pp. 1-17. cited by other |
| Primary Examiner: | Lee, Christopher E. |
| Accession Number: | edspgr.07099973 |
| Database: | USPTO Patent Grants |
| Language: | English |
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