Method of making a semiconductor image sensor
| Title: | Method of making a semiconductor image sensor |
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| Patent Number: | 6,221,686 |
| Publication Date: | April 24, 2001 |
| Appl. No: | 09/493,366 |
| Application Filed: | January 28, 2000 |
| Abstract: | An image sensor (10) has an image sensing element that includes an N-type conducting region (26) and a P-type pinned layer (37). The two regions form two P-N junctions at different depths that increase the efficiency of charge carrier collection at different frequencies of light. The conducting region (26) is formed by an angle implant that ensures that a portion of the conducting region (26) can function as a source of a MOS transistor (32). |
| Inventors: | Drowley, Clifford I. (Phoenix, AZ); Swenson, Mark S. (Higley, AZ); Patterson, Jennifer J. (Mesa, AZ); Ramaswami, Shrinath (Gilbert, AZ) |
| Assignees: | Motorola, Inc. (Schaumburg, IL) |
| Claim: | What is claimed is |
| Claim: | 1. A method of forming an image sensor comprising |
| Claim: | providing a semiconductor substrate of a first conductivity type; |
| Claim: | forming an enhancement layer on the substrate, the enhancement layer having the first conductivity type and a first doping concentration; |
| Claim: | forming a first well on a first portion of the enhancement layer, the first well having the first conductivity type and a second doping concentration that is greater than the first doping concentration wherein the first well has a first depth into the enhancement layer; |
| Claim: | forming a conducting region of a second conductivity type in a second portion of the enhancement layer wherein a first portion of the conducting region forms a portion of a MOS transistor; and |
| Claim: | forming a pinned layer of the first conductivity type in the second region of the enhancement layer by forming a first portion of the pinned layer within the conducting region and a second portion of the pinned layer extending laterally from the conducting region in a direction away from the MOS transistor. |
| Claim: | 2. The method of claim 1 wherein providing the substrate includes providing the substrate with a third doping concentration greater than the first and second doping concentrations. |
| Claim: | 3. The method of claim 1 wherein forming the conducting region includes implanting a first dopant at a first angle from normal to the substrate and angled toward the MOS transistor. |
| Claim: | 4. The method of claim 3 wherein implanting the first dopant at the first angle includes using an angle of at least fifteen degrees. |
| Claim: | 5. The method of claim 3 wherein implanting the first dopant at the first angle includes implanting a first doping concentration substantially normal to the substrate and implanting a second doping concentration at the first angle. |
| Claim: | 6. The method of claim 5 wherein the first doping concentration is implanted at a first energy and the second doping concentration is implanted at a second energy. |
| Claim: | 7. The method of claim 3 wherein the steps of forming the conducting region and forming the pinned layer of the first conductivity type includes implanting the conducting region by implanting the first dopant at the first angle away from normal to the substrate and toward the MOS transistor and implanting the pinned layer at a second angle away from normal to the substrate and away from the MOS transistor. |
| Claim: | 8. The method of claim 7 wherein implanting the first dopant at the first angle includes implanting a first doping concentration substantially normal to the substrate and implanting a second doping concentration at the first angle. |
| Claim: | 9. The method of claim 8 wherein the first doping concentration is implanted at a first energy and the second doping concentration is implanted at a second energy. |
| Claim: | 10. The method of claim 1 wherein forming the conducting region includes forming the conducting region to a depth less than 0.7 microns. |
| Claim: | 11. The method of claim 1 wherein forming the first well includes forming the first well to a first depth no greater than a depth of the enhancement layer. |
| Claim: | 12. The method of claim 1 further including forming a dielectric layer overlying the pinned layer, and forming a silicide layer on a portion of the image sensor wherein an area overlying the pinned layer is devoid of the silicide layer. |
| Claim: | 13. The method of claim 1 further including forming a dielectric layer overlying the pinned layer wherein the dielectric layer has a dielectric constant that is between a dielectric constant of any material overlying the dielectric layer and a dielectric constant of an underlying substrate on which the pinned layer is formed. |
| Claim: | 14. A method of forming an image sensor comprising |
| Claim: | using an implant at a first angle to form a conducting region of the image sensor; and forming a pinned layer at least partially within the conducting region. |
| Claim: | 15. The method of claim 14 further including using a substrate of a first doping concentration, and forming an enhancement layer on the substrate, the enhancement layer having a doping concentration that is less than the first doping concentration wherein the conducting region is formed in the enhancement layer. |
| Claim: | 16. The method of claim 14 further including forming the pinned layer by implanting at a second angle. |
| Claim: | 17. The method of claim 14 further including forming a dielectric layer overlying the pinned layer, and forming a silicide layer on a portion of the image sensor wherein an area overlying the pinned layer is devoid of the silicide layer. |
| Claim: | 18. The method of claim 14 further including forming a dielectric layer overlying the pinned layer wherein the dielectric layer has a dielectric constant that is between a dielectric constant of any material overlying the dielectric layer and a dielectric constant of an underlying substrate on which the pinned layer is formed. |
| Claim: | 19. A method of forming an active pixel sensor comprising |
| Claim: | forming at least one MOS transistor in the first well in the first portion; and |
| Claim: | providing a pinned photodiode in a second portion of the enhancement layer, the pinned photodiode having a first P-N junction at a first depth from the surface, a second P-N junction at a second depth that is less than the first depth, and a conducting region of the second conductivity type between the first depth and the second depth; and |
| Claim: | forming at least one MOS transistor in the second portion of the enhancement layer, such that the pinned photodiode forms a portion of the MOS transistor in the second portion, and a gate of the MOS transistor in the second portion is within the second portion and a drain of the MOS transistor is within the first portion and the second portion. |
| Claim: | 20. The method of claim 19 wherein the step of forming the portion of the MOS transistor in the second portion of the enhancement layer such that the portion of the MOS transistor formed from the pinned photodiode further comprises forming the photodiode portion such that the portion underlies the gate of the MOS transistor. |
| Claim: | 21. The method of claim 20 wherein forming the pinned photodiode includes forming a pinned layer of the first conductivity type in the second portion of the enhancement layer by forming a first portion of the pinned layer within the conducting region of the second conductivity type and a second portion of the pinned layer extending laterally from the conducting region of the second conductivity type in a direction away from the MOS transistor. |
| Claim: | 22. The method of claim 19 wherein providing the substrate includes providing the substrate with a third doping concentration greater than the first and second doping concentrations. |
| Claim: | 23. The method of claim 19 wherein forming the conducting region of the second conductivity type includes implanting a first dopant at a first angle from normal to the substrate and angled toward the MOS transistor. |
| Claim: | 24. The method of claim 23 wherein implanting the first dopant at the first angle includes using an angle of at least fifteen degrees. |
| Claim: | 25. The method of claim 23 wherein implanting the first dopant at the first angle includes implanting a first doping concentration substantially normal to the substrate and implanting a second doping concentration at the first angle. |
| Claim: | 26. The method of claim 25 wherein the first doping concentration is implanted at a first energy and the second doping concentration is implanted at a second energy. |
| Claim: | 27. The method of claim 23 wherein the steps of forming the conducting region and forming the pinned layer of the first conductivity type includes implanting the conducting region by implanting the first dopant at the first angle away from normal to the substrate and toward the MOS transistor and implanting the pinned layer at a second angle away from normal to the substrate and away from the MOS transistor. |
| Claim: | 28. The method of claim 27 wherein implanting the first dopant at the first angle includes implanting a first doping concentration substantially normal to the substrate and implanting a second doping concentration at the first angle. |
| Claim: | 29. The method of claim 28 wherein the first doping concentration is implanted at a first energy and the second doping concentration is implanted at a second energy. |
| Claim: | 30. The method of clam 19 wherein forming the conducting region includes forming the conducting region to a depth less than 0.7 microns. |
| Claim: | 31. The method of claim 19 wherein forming the first well includes forming the first well to a first depth no greater than a depth of the enhancement layer. |
| Claim: | 32. The method of claim 19 further including forming a dielectric layer overlying the pinned photodiode, and forming a silicide layer on a portion of the image sensor wherein an area overlying the pinned photodiode is devoid of the silicide layer. |
| Claim: | 33. The method of claim 19 further including forming a dielectric layer overlying the pinned photodiode wherein the dielectric layer has a dielectric constant that is between a dielectric constant of any material overlying the dielectric layer and a dielectric constant of an underlying substrate on which the pinned photodiode is formed. |
| Claim: | 34. The method of claim 19 further including forming the enhancement layer and first well such that the first well, the enhancement region and the substrate are connected by an ohmic conduction path below the surface of the semiconductor. |
| Current U.S. Class: | 438/57; 438/66; 438/69; 438/72; 438/73; 257/290; 257/292; 257/293 |
| Current International Class: | H01L 2100 |
| Patent References Cited: | 3887993 June 1975 Okada et al. 4484210 November 1984 Shiraki et al. 4735680 April 1988 Yen 4868623 September 1989 Nishiura 5191399 March 1993 Maegawa 5216491 June 1993 Yamamoto et al. 5585653 December 1996 Nakashiba 5625210 April 1997 Lee et al. 6100556 August 2000 Drowley et al. |
| Other References: | "The Pinned Photodiode for an Interline-Transfer CCD Image Sensor", B. C. Burkey et al., IEDM-84, Section 2.3, pp. 28-31. "Microelectronic Devices", Edward S. Young, McGraw-Hill Book Co., 1988, p. 63. "Physics of Semiconductor Devices", Second Edition, S.M. Sze, John Wiley & Son, Inc. 1981, p. 66. "Device Electronics for Integrated Circuit", Second Edition, Richard S. Muller, John Wiley & Son, Inc., 1981, p. 94. "Physics of Semiconductor Devices", S.M. Sze, A. Wiley Interscience Publication, 1981, pp. 754, 759,760. |
| Primary Examiner: | Bowers, Charles |
| Assistant Examiner: | Kielin, Erik J. |
| Attorney, Agent or Firm: | Huffman, A. Kate |
| Accession Number: | edspgr.06221686 |
| Database: | USPTO Patent Grants |
| Language: | English |
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