Dual level wordline clamp for reduced memory cell current
| Title: | Dual level wordline clamp for reduced memory cell current |
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| Patent Number: | 5,936,894 |
| Publication Date: | August 10, 1999 |
| Appl. No: | 09/094,786 |
| Application Filed: | June 15, 1998 |
| Abstract: | The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size. |
| Inventors: | Hawkins, Andrew L. (Santa Clara, CA); Hunt, Jeffery Scott (Ackerman, MS); Saripella, Satish C. (Starkville, MS); Sunder, Sanjay (Starkville, MS) |
| Assignees: | Cypress Semiconductor Corp. (San Jose, CA) |
| Claim: | We claim |
| Claim: | 1. A circuit comprising |
| Claim: | a wordline; and |
| Claim: | a clamp circuit configured to generate a first voltage on said wordline during a read operation and a second voltage on said wordline during a write operation, wherein said first and second voltages are different voltages each generated in response to a select signal. |
| Claim: | 2. The circuit of claim 1, whererin said first and second voltages are less than a supply voltage. |
| Claim: | 3. The circuit according to claim 2, wherein said select signal is coupled to one or more devices coupled to said wordline. |
| Claim: | 4. The circuit according to claim 3 wherein |
| Claim: | a first state of said select signal corresponds to said read operation; and |
| Claim: | a second state of select signal corresponds to said write operation. |
| Claim: | 5. The circuit according to claim 1 wherein said clamp circuit comprises one or more transistors. |
| Claim: | 6. The circuit of claim 5 wherein said one or more transistors couple said wordline to a ground voltage. |
| Claim: | 7. The circuit according to claim 1 wherein said clamp circuit comprises one or more diodes. |
| Claim: | 8. The circuit according to claim 1 wherein said clamp circuit comprises dual level wordline clamp. |
| Claim: | 9. The circuit according to claim 1 further comprising a memory cell coupled to said wordline. |
| Claim: | 10. The circuit of claim 9, wherein said memory cell comprises a random access memory (RAM) cell. |
| Claim: | 11. The circuit according to claim 10 wherein said RAM cell comprises a Static Random Access Memory (SRAM) cell. |
| Claim: | 12. A circuit comprising |
| Claim: | wordline means; and |
| Claim: | means for clamping a first voltage on said wordline means during a read operation and a second voltage on said wordline means during a write operation, wherein said first and second voltages are different voltages each generated in response to a selected signal. |
| Claim: | 13. The circuit according to claim 12 wherein said first and second voltages are less than a supply voltage. |
| Claim: | 14. The circuit according to claim 13 wherein said clamping means comprises one or more transistors. |
| Claim: | 15. The circuit according to claim 12 further comprising |
| Claim: | select means coupled to said wordline means, said select means corresponding to an operational mode of an external circuit. |
| Claim: | 16. The circuit according to claim 15 wherein |
| Claim: | a first state of said select means corresponds to said read operation; and |
| Claim: | a second state of said select means corresponds to said write operation. |
| Claim: | 17. The circuit according to claim 12 wherein said clamping means comprises one or more diodes. |
| Claim: | 18. The circuit according to claim 12 further comprising a Static Random Access Memory (SRAM) cell coupled to said wordline means. |
| Claim: | 19. A method for reducing current consumption in a memory comprising the steps of |
| Claim: | (a) clamping a first voltage to a wordline in a memory cell in said memory in response to a first state of a control signal; and |
| Claim: | (b) clamping a second voltage to said wordline in response to a second state of said control signal, wherein said first and second voltages are different voltages. |
| Claim: | 20. The method according to claim 19, wherein |
| Claim: | a second state of said select signal corresponds to said write operation. |
| Current U.S. Class: | 36518/906; 36518/909; 36518/911 |
| Current International Class: | G11C 1604 |
| Patent References Cited: | 4074237 February 1978 Spampinato 4156941 May 1979 Homma et al. 4546457 October 1985 Nozaki et al. 5287307 February 1994 Fukuda et al. 5333122 July 1994 Ninomiya 5796651 August 1998 Horne et al. |
| Primary Examiner: | Nelms, David |
| Assistant Examiner: | Lam, David |
| Attorney, Agent or Firm: | Maiorana, P.C., Christopher P. |
| Accession Number: | edspgr.05936894 |
| Database: | USPTO Patent Grants |
| Language: | English |
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