Method and apparatus for simulating banked memory as a linear address space
| Title: | Method and apparatus for simulating banked memory as a linear address space |
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| Patent Number: | 5,734,858 |
| Publication Date: | March 31, 1998 |
| Appl. No: | 08/327,971 |
| Application Filed: | October 24, 1994 |
| Abstract: | A method and apparatus for providing access to a banked peripheral memory via a contiguous linear address space. The present invention provides a linear address space having a present region that is mapped to a host memory region of a computer system. The present invention further provides a relocatable selector that provides access to a portion of the linear address space. Accessing programs exchange data with the banked peripheral memory via the relocatable linear address space. When an accessing program references an address of the relocatable address base that is not mapped to the present region, the relocatable linear address space is positioned so that the referenced address maps to the present region. Additionally, a bank of the peripheral memory that corresponds to the referenced address is also mapped into the host memory region so as to enable the accessing program to exchange data with the banked peripheral memory via the relocatable linear address space. |
| Inventors: | Patrick, Stuart R. (Issaquah, WA); Pletcher, Richard A. (Redmond, WA); Gibson, Michael S. (Redmond, WA); Chatterjee, Amit (Redmond, WA) |
| Assignees: | Microsoft Corporation (Redmond, WA) |
| Claim: | We claim |
| Claim: | 1. In a computer system having a central processing unit that provides a paging mechanism for mapping virtual pages to physical pages, the paging mechanism utilizing a page table entry for each of the virtual pages, each page table entry containing a field for specifying a location of a physical page, a peripheral memory that is comprised of a plurality of banks, a main memory having a host memory region that is formed by a predetermined number of physical pages so that the host memory region allows access to only a fraction of the banks of the peripheral memory at any one time, a method for providing access to the peripheral memory, the method comprising the steps of |
| Claim: | providing a linear address space that is formed by a plurality of virtual pages, the linear address space having a present region that is formed by mapping at least one of the virtual pages to one of the physical pages of the host memory region; |
| Claim: | providing a segment selector for a segment, wherein the segment has a size that approximates a size of the peripheral memory; |
| Claim: | receiving a peripheral memory access request; |
| Claim: | determining a bank of the peripheral memory that is needed to satisfy the peripheral memory access request; |
| Claim: | mapping the needed bank into the host memory region; and |
| Claim: | assigning a value to the segment selector in the linear address space so as to satisfy the peripheral memory access requests without modifying the page table entries of the linear address space. |
| Claim: | 2. The method of claim 1 wherein the segment selector comprises a base address for specifying a position of the segment and wherein the step of assigning a value to the segment selector in the linear address space so as to satisfy the peripheral memory access requests without modifying the page table entries of the linear address space comprises the steps of |
| Claim: | determining a region of the segment that simulates the needed bank; and |
| Claim: | adjusting the base address of the segment selector, so that the determined region of the segment maps to the present region of the linear address space. |
| Claim: | 3. The method of claim 1 wherein the linear address space is approximately twice the size of the peripheral memory and wherein the present region of the linear address space is positioned at an approximate midpoint of the linear address space. |
| Claim: | 4. In a computer system having a hardware window that permits a program module to access only a fraction of a total amount of an addressable memory at a time, a method for allowing the module to address the addressable memory as a contiguous linear buffer, the method comprising the steps of |
| Claim: | reserving an address space that is at least equal in size with the addressable memory; |
| Claim: | mapping a portion of the reserved address space to the hardware window; |
| Claim: | providing a linear representation of the addressable memory by allocating a linear address segment having a predetermined size that is approximately equal to the total amount of the addressable memory, the linear representation of the addressable memory serving as an interface between the module and the addressable memory; |
| Claim: | positioning the linear address segment so that it is mapped within the reserved address space; |
| Claim: | determining when the program module is attempting to access an address of the linear address segment that does not translate to the mapped portion of the reserved address space; |
| Claim: | determining an address of the addressable memory that corresponds to the address of the linear address segment that the program module is attempting to access; |
| Claim: | mapping the determined address of the addressable memory into the hardware window; and |
| Claim: | repositioning the linear address segment so that the address of the linear address segment that the program module is attempting to access maps to the determined address of the addressable memory. |
| Claim: | 5. The method of claim 4 wherein the linear address segment comprises a base address field for specifying a starting address of the linear address segment, and wherein the step of repositioning the linear address segment comprises the step of |
| Claim: | modifying the base address of the linear address segment. |
| Claim: | 6. The method of claim 4 wherein the reserved linear address space is approximately twice as large as the addressable memory, and wherein the portion of the reserved address space that is mapped to the hardware window is positioned approximately midway in the reserved linear address space. |
| Claim: | 7. In a computer system having a central processing unit that provides a paging mechanism for translating virtual pages to physical pages, a peripheral memory formed by a plurality of banks, and a main memory having a host access region for switching the banks of the peripheral memory into the main memory, a method for simulating the peripheral memory as a contiguous memory buffer to allow a program module to access the peripheral memory without requiring the module to conduct any bank switching or to respond to any page faults, the method comprising the steps of |
| Claim: | reserving a first linear address space, the first linear address space being comprised of a plurality of virtual pages; |
| Claim: | forming a present region within the first linear address space by mapping a predetermined number of the plurality of virtual pages to the host access region; |
| Claim: | allocating a second linear address space in which a peripheral memory access request is received from the program module; and |
| Claim: | providing a page fault handler to determine a bank of the peripheral memory that is needed to satisfy the peripheral memory access request, to map the needed bank into the host access region, to determine a portion of the second linear address space that simulates the needed bank, and to position the second linear address space within the first linear address space so that the determined portion of the second linear address space maps to the host access region via the present region of the first linear address space. |
| Claim: | 8. The method of claim 7 wherein the second linear address space comprises a base address for specifying a position of the second linear address space and wherein the page fault handler positions the second linear address space within the first linear address space by modifying the base address. |
| Claim: | 9. The method of claim 7 wherein the first linear address space is approximately twice the size of the peripheral memory and wherein the present region of the first linear address space is positioned at an approximate midpoint of the first linear address space. |
| Claim: | 10. In a computer system having a peripheral memory that is formed by a plurality of banks, a designated memory region that provides access to only a fraction of the plurality of banks at any given time, an apparatus for simulating simultaneous access to the plurality of banks, the apparatus comprising |
| Claim: | a linear address space having a portion that is mapped to the designated memory region |
| Claim: | a sliding address segment that is positioned within the linear address space, wherein the sliding address segment simulates the plurality of memory banks as a continuous linear memory buffer and receives a peripheral memory access request; and |
| Claim: | a fault handler that determines, from the plurality of banks, a bank that is needed to satisfy the peripheral memory access request, maps the needed bank to the designated memory region, determines a portion of the sliding address segment that corresponds to the needed bank, and adjusts the positioning of the sliding address segment so that the portion of the sliding address segment that corresponds to the needed bank maps to the designated memory region. |
| Claim: | 11. The apparatus of claim 10 wherein the sliding address segment has a base address, and wherein the fault handler adjusts the positioning of the sliding address segment by its base address. |
| Claim: | 12. The apparatus of claim 10 wherein the linear address space is approximately twice the size of the sliding address segment, and wherein the present region is positioned at the approximate midpoint of the linear address space. |
| Claim: | 13. The apparatus of claim 10 wherein the computer system further comprises an operating system, wherein the fault handler is an operating system and wherein the peripheral memory access request is received from a device driver. |
| Claim: | 14. In a computer system having a host memory region for providing access to a limited region of a banked peripheral memory, the banked peripheral memory being formed by a plurality of banks, a method for providing access to the banked peripheral memory, the method comprising the steps of |
| Claim: | providing a segment selector for a segment that simulates the banked peripheral memory as a contiguous linear buffer; |
| Claim: | providing a linear address space in which the provided segment selector is positioned; |
| Claim: | mapping a portion of the provided linear address space to the host memory region; |
| Claim: | receiving memory access requests from accessing modules, the received memory access request referencing an address in the provided segment; and |
| Claim: | when the referenced address of the provided segment selector is not mapped to the portion of the linear address space that is mapped to the host memory region |
| Claim: | positioning the segment selector so that the referenced address maps to the portion of the linear address space that is mapped to the host memory region |
| Claim: | determining a bank, from among the plurality of banks that form the banked peripheral memory, that contains a memory location that is simulated by the referenced address of the memory access request, and |
| Claim: | mapping the determined bank to the host memory region. |
| Claim: | 15. The method of claim 14 wherein the step of mapping the determined bank to the host memory region comprises the step of |
| Claim: | mapping the memory location that is simulated by the referenced address of the memory access request to the approximate midpoint of the host memory region. |
| Claim: | 16. In a computer system having a host memory region that provides access to a portion of a banked peripheral memory that is formed by a plurality of banks, a method for responding to a memory access request received from a program module, the memory access request being for an address in a segment that is identified by a segment selector and that simulates the banked peripheral memory as a contiguous buffer, the memory access request specifying an address that the program module desires to access, the selector being positioned within a linear address space having a present region that is mapped to the host memory region, the method comprising the step of |
| Claim: | when the desired address of the received memory access request is an address that simulates memory locations of the banked peripheral memory that cross a bank boundary, the bank boundary being defined by an ending memory location of a first bank and a starting memory location of a second bank |
| Claim: | sliding the selector in the linear address space so that the desired address of the memory access request maps to the host memory region; |
| Claim: | deconstructing the received memory access request into a first part and a second part, wherein the first part of the deconstructed memory access request references only memory locations contained in the first bank and wherein the second part of the deconstructed memory access request references only memory locations of the second bank |
| Claim: | mapping the first bank into the host memory region to respond to the first part of the deconstructed memory access request, and |
| Claim: | mapping the second bank into the host memory region to respond to the second part of the deconstructed memory access request. |
| Claim: | 17. In a computer system having a host memory region that provides limited access to a banked peripheral memory through a host memory region of a main memory, wherein the banked peripheral memory is formed by a plurality of banks, an apparatus that permits a program module to easily access the banked peripheral memory, the apparatus comprising |
| Claim: | means for receiving, from the program module, a memory access request in a segment that is identified by a segment selector and that simulates the banked peripheral memory as a linear buffer, the memory access request providing a desired address of the segment that the program module wishes to access wherein the desired address simulates a corresponding memory location of the banked peripheral memory; |
| Claim: | means for positioning, in response to the received memory access request, the segment selector in a linear address space that is partially mapped to the host memory region; |
| Claim: | means for determining a bank of the banked peripheral memory that is needed to satisfy the memory access request; and |
| Claim: | means for mapping the determined bank to the host memory region. |
| Claim: | 18. The apparatus of claim 17 wherein the means for mapping the determined bank to the host memory region comprises |
| Claim: | means for mapping the corresponding memory location of the banked peripheral memory to the approximate midpoint of the host memory region. |
| Claim: | 19. The apparatus of claim 17 wherein the linear address space is approximately twice the size of the banked peripheral memory. |
| Claim: | 20. In a computer system having a host memory region that provides access to a limited region of a banked peripheral memory that is formed by a plurality of banks, a method for providing access to the banked peripheral memory, the method comprising the steps of |
| Claim: | providing a first segment selector for a first segment and a second selector for a second segment wherein each segment simulates the banked peripheral memory as a contiguous linear buffer, wherein the first segment selector is used in servicing an input peripheral memory access request, and wherein the second segment selector is used in servicing an output peripheral memory access request, each respective peripheral memory access request referencing an address of the respective selector that the module desires to access; |
| Claim: | providing a linear address space in which the provided segment selectors are positioned; |
| Claim: | after receiving the input peripheral memory access request |
| Claim: | determining whether the referenced address of the first segment selector is mapped to the portion of the linear address space that is mapped to the host memory region; |
| Claim: | when the referenced address of the first segment selector is not mapped to the portion of the linear address space that is mapped to the host memory region |
| Claim: | positioning the first segment selector so that the referenced address maps to the portion of the linear address space that is mapped to the host memory region |
| Claim: | determining a bank, from among the plurality of banks that form the banked peripheral memory, that contains a memory location that is simulated by the referenced address of the input peripheral memory access request, and |
| Claim: | mapping the determined bank to the host memory region; and after receiving the output peripheral memory access request |
| Claim: | determining whether the referenced address of the second segment selector is mapped to the portion of the linear address space that is mapped to the host memory region; |
| Claim: | when the referenced address of the second segment selector is not mapped to the portion of the linear address space that is mapped to the host memory region |
| Claim: | positioning the second segment selector so that the referenced address maps to the portion of the linear address space that is mapped to the host memory region |
| Claim: | discerning a bank, from among the plurality of banks that form the banked peripheral memory, that contains a memory location that is simulated by the referenced address of the output peripheral memory access request, and |
| Claim: | mapping the discerned bank to the host memory region. |
| Claim: | 21. The method of claim 20 wherein the step of mapping the determined bank to the host memory region |
| Claim: | 22. In a computer system having a central processing unit that provides a paging mechanism for mapping virtual pages to physical pages, the paging mechanism utilizing a page table entry for each of the virtual pages, each page table entry containing a field for specifying a location of a physical page, a peripheral memory that is comprised of a plurality of banks, a main memory having a host memory region that is formed by a predetermined number of physical pages so that the host memory region allows access to only a fraction of the banks of the peripheral memory at any one time, a computer-readable medium holding computer-executable instructions for performing a method for providing access to the peripheral memory, the method comprising the steps of |
| Claim: | providing a segment selector for a segment that is sized such that it approximates the peripheral memory; |
| Claim: | mapping the needed bank into the host memory region; and assigning a value to the segment selector in the linear address space so as to satisfy the peripheral memory access requests without modifying the page table entries of the linear address space. |
| Claim: | 23. The computer-readable medium of claim 22 wherein the segment selector comprises a base address for specifying a position of the segment and wherein the step of assigning a value to the segment selector in the linear address space so as to satisfy the peripheral memory access requests without modifying the page table entries of the linear address space comprises the steps of |
| Claim: | 24. In a computer system having a hardware window that permits a program module to access only a fraction of a total amount of an addressable memory at a time, a computer-readable medium holding computer-executable instructions for performing a method for allowing the module to address the addressable memory as a contiguous linear buffer, the method comprising the steps of |
| Claim: | 25. The computer-readable medium of claim 24 wherein the linear address segment comprises a base address field for specifying a starting address of the linear address segment, and wherein the step of repositioning the linear address segment comprises the step of |
| Claim: | 26. The computer-readable medium of claim 24 wherein the reserved linear address space is approximately twice as large as the addressable memory, and wherein the portion of the reserved address space that is mapped to the hardware window is positioned approximately midway in the reserved linear address space. |
| Claim: | 27. In a computer system having a hardware window that permits a program module to access only a fraction of a total amount of an addressable memory at a time, a computer-readable medium holding computer-executable instructions for performing a method for allowing the module to address the addressable memory as a contiguous linear buffer, the method comprising the steps of |
| Claim: | 28. The computer-readable medium of claim 27 wherein the second linear address space comprises a base address for specifying a position of the second linear address space and wherein the page fault handler positions the second linear address space within the first linear address space by modifying the base address. |
| Claim: | 29. The computer-readable medium of claim 27 wherein the first linear address space is approximately twice the size of the peripheral memory and wherein the present region of the first linear address space is positioned at an approximate midpoint of the first linear address space. |
| Claim: | 30. In a computer system having a host memory region for providing access to a limited region of a banked peripheral memory, the banked peripheral memory being formed by a plurality of banks, a computer-readable medium holding computer-executable instructions for performing a method for providing access to the banked peripheral memory, the method comprising the steps of |
| Claim: | 31. The computer-readable medium of claim 30 wherein the step of mapping the determined bank to the host memory region comprises the step of |
| Claim: | 32. In a computer system having a host memory region that provides access to a limited region of a banked peripheral memory that is formed by a plurality of banks, a computer-readable medium holding computer-executable instructions for performing a method for providing access to the banked peripheral memory, the method comprising the steps of |
| Current U.S. Class: | 395/412; 395/402; 395/405; 395/404; 395/415; 395/412; 395/416; 395/417; 395/418 |
| Current International Class: | G06F 926; G06F 1202; G06F 1204; G06F 1210 |
| Patent References Cited: | 4926322 May 1990 Stimac et al. 5249280 September 1993 Nash et al. 5255382 October 1993 Pawloski 5321425 June 1994 Chia et al. |
| Other References: | Statement Describing a Conventional System. |
| Primary Examiner: | Downs, Robert W. |
| Assistant Examiner: | Nguyen, Than V. |
| Attorney, Agent or Firm: | Seed and Berry LLP |
| Accession Number: | edspgr.05734858 |
| Database: | USPTO Patent Grants |
| Language: | English |
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