VLSI Wired-OR driver/receiver circuit
| Title: | VLSI Wired-OR driver/receiver circuit |
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| Patent Number: | 4,500,988 |
| Publication Date: | February 19, 1985 |
| Appl. No: | 06/355,803 |
| Application Filed: | March 08, 1982 |
| Abstract: | Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines. |
| Inventors: | Bennett, Donald B. (Burnsville, MN); Thorsrud, Lee T. (Saint Paul, MN); Petschauer, Thomas W. (Bloomington, MN) |
| Assignees: | Sperry Corporation (New York, NY) |
| Claim: | What is claimed is |
| Claim: | 1. The method of driving a communications bus line connecting a plurality of driver/receiver elements, said communication bus line having inherent capacitance, said method comprising |
| Claim: | applying a first signal to said bus line during a first time interval from each and all of said driver/receiver elements in order to drive said bus line to a first voltage level representing a first logic state; and |
| Claim: | applying a second signal to said bus line during a second time interval from those ones of said driver/receiver elements which desire to drive said bus line to a second voltage level representing a second logic state, said second signal as applied from any one or ones of said driver/receiver elements which desire to drive said bus line to said second voltage level being sufficient to do so drive said bus line to said second voltage level; |
| Claim: | wherein if none of those said ones of said driver/receiver elements do desire to drive said bus line to said second voltage level then said inherent capacitance of said bus line will maintain said bus line substantially at said first voltage level representing said first logical state for at least a portion of said second time interval. |
| Claim: | 2. The method of driving a communications bus line of claim 1 wherein said applying a first signal further comprises |
| Claim: | applying a first signal to drive said bus line to a non-zero voltage level representing a binary logical state of "0"; |
| Claim: | and wherein said applying a second signal further comprises |
| Claim: | applying a second signal to drive said bus line to a zero voltage level representing a binary logical state of "1" |
| Claim: | wherein all said driver/receiver elements are connected wired-OR upon and by said bus line, said wired-OR meaning that IF any one of said driver/receiver elements does desire to and does drive said bus line to said zero voltage level representing a binary logical state of "1" THEN said any one driver/receiver element which does drive said bus line to said zero voltage level will establish that the entire said busline is at said binary logical state of "1", and ONLY IF none of said driver/receiver elements does desire to or does drive said bus line to said zero voltage level THEN said inherent capacitance of said bus line will maintain said bus line substantially at said non-zero voltage level representing said binary logical state of "0" for at least said portion of said second time interval. |
| Claim: | 3. A method of communicating between a plurality of driver/receiver elements interconnected on a single signal line which signal line is part of a communication bus containing a plurality of such signal lines interconnecting a plurality of devices, which method conmprises |
| Claim: | first current-driving said interconnecting signal line to a non-zero voltage condition from all said interconnected driver/receiver elements during a first period of time, which first period of time is common to all said interconnected driver/receiver elements; then |
| Claim: | terminating all said first current drive from all said driver/receiver elements to said interconnecting signal line at a time ending said first period; then |
| Claim: | independently at each interconnected driver/receiver element during a second period of time immediately following said first period of time either (1) allowing the capacitance of said interconnecting signal line to maintain said signal line at substantially said non-zero voltage condition, in the case that said each interconnected driver/receiver element does not wish to transmit information OR wishes to transmit binary "0" information, or else (2) second current-driving said interconnecting signal line toward a zero voltage condition in the case that said each interconnected driver/receiver element wishes to transmit binary "1" information; while also during second period of time |
| Claim: | sensing said interconnecting signal line at all said interconnected driver/receiver elements in order that it may be recognized if said interconnecting signal line continues substantially unchanged at said non-zero voltge condition or whether said interconnecting signal line has been second current-driven toward a zero voltage condition by said second current-driving at some one(s) of said interconnected driver/receiver elements; while also during said second period of time |
| Claim: | interpreting at all said interconnected driver/receiver elements said sensing of said interconnecting signal line to continue substantially unchanged at said non-zero voltage condition to mean that said interconnecting signal line has transmitted during said second period of time a binary "0" and said sensing that said interconnecting signal line has been second current-driven toward a zero voltage condition to mean that said interconnecting signal line has transmitted during said second period of time a binary "1". |
| Claim: | 4. The communication method of claim 3 wherein further comprises: disconnecting all current drive from any and all of said interconnected driver/receiver elements to said interconnecting signal line at the end of said second period of time; |
| Claim: | wherein said first current-driving may be subsequently reinitiated and cyclic communication transpire. |
| Claim: | 5. The communication method of claim 3 or claim 4 wherein (1) said first current-driving transpiring during said first period of time, and (2) either said allowing said capacitance of said interconnecting signal line to maintain said signal line at substantially said non-zero voltage condition or said second current-driving said interconnecting signal line toward said zero voltage condition transpiring during said second period of time, and (3) said sensing also transpiring during said second period of time, all transpire within forty nanoseconds, meaning that said first period of time plus said second period of time is less than or equal to forty nanoseconds. |
| Claim: | 6. The communication method of claim 3 wherein said interpreting step further comprises |
| Claim: | interpreting at all said interconnected driver/receiver elements said sensing of the continuation of said interconnection signal line substantially unchanged at said non-zero voltage condition as the transmission of a binary "0" upon said interconnecting signal line, or else said sensing of said interconnecting signal line to have been second current-driven toward a zero voltage condition as the transmission of a binary "1" upon said interconnecting signal line; |
| Claim: | wherein since one or more of said interconnected driver/receiver elements may perform said second current-driving then said interpreting at all said interconnected driver/receiver elements will be of the transmission of a binary "0" only if no one of any said driver/receiver elements has second current-driven said interconnecting signal line toward a zero voltage condition, but will be of the transmission of a binary "1" if any one or ones of said driver/receiver elements has driven said interconnecting signal line toward a zero voltage condition; |
| Claim: | whereby any one of said driver/receiver elements can cause the transmission of a binary "1", but all said driver/receiver elements must identically restrain from second current-driving said interconnecting signal line to cause the transmission of a binary "0", which transmission is thusly logically wired-OR between all said driver/receiver elements. |
| Claim: | 7. A digital bus line driver apparatus for receiving voltage, ground, a universal two-phase clock signal, and an individually unique binary-stated data signal, and for synchronously driving responsively to said individually unique binary-stated data signal a digital communication bus line interconnecting a plurality of like digital bus line driver apparatus, each said apparatus comprising |
| Claim: | bus line charging means between said voltage and said bus line for, responsively to a first phase of said universal two-phase clock signal, conductively charging from said voltage said bus line to substantially said voltage during said first phase, and for not conducting and presenting high impedance to said bus line during a second phase of said universal two-phase clock signal, in series with; |
| Claim: | busline selective discharging means between said bus line and said ground for not conducting and presenting high impedance to said bus line during said first phase of said universal two-phase clock signal, and, for IF a first, true, binary state is resultant from the logical ANDing of said individually unique binary-stated data signal and said second phase of said universal two-phase clock signal, THEN conductively discharging said bus line substantially to ground meaning zero voltage during said second phase of said universal two-phase clock signal, ELSE IF a second, false, binary state is resultant from said logical ANDing THEN not conductively discharging said bus line substantially to ground and continuing presenting high impedance to said bus line; |
| Claim: | wherein said conductively charging of said bus line does thusly invariably transpire jointly from all said plurality of like digital bus line driver apparatus, which apparatus are interconnected by said bus line, during said first phase of said universal two-phase clock; |
| Claim: | wherein said conductively discharging of said bus line will transpire from only those one or ones, if any, of said plurality of like digital bus line driver apparatus wherein said first, true, binary state is resultant from said logical ANDing of said individually unique binary-stated data signal and said second phase of said universal two-phase clock signal. |
| Claim: | 8. The digital bus line driver apparatus of claim 7 which further comprises |
| Claim: | pull-up means of high resistance between said voltage and said bus line for always providing small current from said voltage for charging said bus line from said voltage to a non-zero voltage; |
| Claim: | wherein only said small current will be provided from said voltage to said bus line when and if said bus line is conductively discharged to ground by one or ones of said bus line selective discharging means which are within each of said plurality of digital bus line driver apparatus which are interconnected by said digital communication bus line. |
| Claim: | 9. A line driver apparatus for receiving a first time phasesignal, a second time phase signal, a data signal, and a source of voltage and ground and for driving a communication line in response thereto, which apparatus comprises |
| Claim: | gating means for logically ANDing said second time phase signal and said data signal into a second time phase gated-data signal; |
| Claim: | a first field effect transistor means for invariably current driving only during a first time phase signal a communication line means toward the voltage of said source of voltage, the source terminal thereof said first field effect transistor means connected to said source of voltage, with the base terminal thereof connected to said first time phase signal, and with the drain terminal thereof series connected to |
| Claim: | a second field effect transistor means for current sinking during said second time phase gated data signal a charged output communication line means towards said ground, the source terminal thereof said second field effect transistor means connected to said drain terminal of said first field effect transistor means, with the base treminal thereof connected to said second time phase gated-data signal developed by said gating means, and with the drain terminal connected to ground; |
| Claim: | output communication line means connected to said first field effect transistor means and said second field effect transistor means at their series interconnect point for transmitting current driven toward said source of voltage by said first field effect transistor means during said first time phase signal, and for transmitting current sinked toward said ground by said second field transistor means during said second time phase gated signal, to current receiver means; and |
| Claim: | current receiver means for receiving current transmitted by said output communication line means. |
| Claim: | 10. The apparatus according to claim 9 which further comprises |
| Claim: | resistor means between said source of voltage and said output communication line means. |
| Claim: | 11. A line driver apparatus for always driving a signal line to a non-zero voltage during a first period, and for dependently upon the alternative states of a binary data signal, either presenting high impedance to said signal line or else driving said signal line to a zero voltage during a second period; said apparatus comprising |
| Claim: | timing means for supplying a first period signal followed by a second period signal; |
| Claim: | a non-zero voltage source means for supplying non-zero voltage; |
| Claim: | a zero voltage ground source means for supplying zero voltage ground; |
| Claim: | a first field effect transistor means between said non-zero voltage source means and said signal line with the gate thereof said first field effect transistor means connected to said timing means for, responsively to said first period signal followed by said second period signal driving said signal line from said non-zero voltage source during said first period while presenting a high impedance between said signal line and said voltage source elsetimes; |
| Claim: | logical AND gate means for logically ANDing said second period signal AND said data signal; and |
| Claim: | a second field effect transistor means between said zero voltage ground source means and said signal line with the gate thereof said second field effect transistor means connected to said logical AND gate means for, responsively to the logical ANDing of both said second period signal and said data signal within said logical AND gate means, IF both said second period signal and said binary data signal are of the logically true, or "1", binary state THEN driving said signal line toward said zero voltage ground ELSE IF either said second period signal or said binary data signal is of the logically false, or "0", binary state THEN presenting a high impedance between said signal line and said zero voltage ground source means. |
| Claim: | 12. A wired-OR bus interconnection system comprising |
| Claim: | a data bus line; |
| Claim: | a plurality of driver/receiver elements connected to said data bus line; |
| Claim: | means producing sequences of first and second clock signals |
| Claim: | each said driver/receiver element including first means responsive to said first clock signals to drive said data bus line to a first voltage level representing a first logic state, each of said driver/receiver elements being simultaneously responsive to each of said first clock signals, and |
| Claim: | each said driver/receiver element including a second means responsive to said second clock signals for driving said data bus line to a second voltage level representing a second logic state if said driver/receiver element receives a data signal during the presence of said second clock signals and |
| Claim: | means for selectively applying data signals to said second means in each of said driver/receiver elements. |
| Claim: | 13. A bus line driver apparatus which is replicated at the situs of each of a plurality of devices, said replicated bus line driver apparatus being interconnected by a bus line, each said replicated bus line driver apparatus implemented in Complementary Metal oxide Semiconductor (CMOS) technology, each said replicated bus line driver apparatus comprising |
| Claim: | first transistor means implemented in CMOS technology for charging said bus line to a non-zero voltage; series connected with |
| Claim: | second transistor means implemented in CMOS technology for discharging said busline to a zero voltage; |
| Claim: | wherein a first said first transistor means part of a first said bus line driver apparatus is jointly operative with a second said first transistor means part of a second said bus line driver apparatus to jointly charge said bus line to a non-zero voltage of magnitude of 3 volts d.c. within eight nanoseconds if and when said bus line is possessed of no more than 256 picofarads of capacitance essentially physically uniformly distributed along a voltage propagation path of length up to one meter; |
| Claim: | wherein said first transistor means within each and every said replicated bus line driver apparatus are always simultaneously jointly and collectively operative during a first time period longer than said eight nanoseconds for collectively charging said bus line to a non-zero voltage. |
| Claim: | 14. The bus line driver apparatus according to claim 13 wherein each said individual one of said second field effect transistor means within each individual one said replicated bus line driver apparatus is individually capable of discharging up to 256 picofarads of capacitance essentially physically uniformly distributed along a voltage propagation path of length up to one meter charged to a magnitude of three volts d.c. to said zero voltage ground level of within 20 nanoseconds; and |
| Claim: | wherein two or more of said second transistor means each within a said replicated bus line driver apparatus MAY SOMETIMES by being simultaneously jointly and collectively operative during second time periods greater than said twenty nanoseconds, separate from said first time periods, discharge said bus line to said zero voltage ground level BUT UPON AT LEAST ONE of said second time periods a single individul one of said second transistor means within a single individual one said replicated bus line driver apparatus will individually discharge said bus line to said zero voltage level. |
| Claim: | 15. The bus line driver apparatus of claim 13 wherein said up to 256 picofarads of capacitance encompasses individual capacitances additive from any or all of the following sources |
| Claim: | up to one meter of standard unshielded printed circuit land upon a dielectric substrate; and |
| Claim: | up to eighteen further replications, beyond said first and said second bus driver apparatus, of said bus driver apparatus, which may be powered or not in any combination, essentially physically uniformly distributed along said bus line; and |
| Claim: | up to two receiver logic elements, said logic elements being of the typical capacitance of an inverter or an OR gate implemented in CMOS technology associated with each of said first and said second and said up to eighteen replications of said bus driver apparatus as are essentially evenly physically uniformly distributed along said bus line; and |
| Claim: | parasitic capacitances associated with the normal interconnections made between each of the priorly listed sources; |
| Claim: | wherein an actually physically realizable useful structure of up to twenty bus-line-interconnected devices is encompassable within 256 picofarads of capacitance which capacitance is chargeable to said non-zero voltage by two of said first field effect transistor means jointly operative to do so. |
| Current U.S. Class: | 370/85; 375/36 |
| Current International Class: | H03K 1700 |
| Patent References Cited: | 4024501 May 1977 Herring et al. 4101734 July 1978 Dao 4216389 August 1980 Carter 4337465 June 1982 Spracklen et al. 4388725 June 1983 Saito et al. |
| Primary Examiner: | Olms, Douglas W. |
| Assistant Examiner: | Rokoff, Kenneth I. |
| Attorney, Agent or Firm: | Fuess, William C. Grace, Kenneth T. Truex, Marshall M. |
| Accession Number: | edspgr.04500988 |
| Database: | USPTO Patent Grants |
| Language: | English |
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