Bibliographic Details
| Title: |
Gain control circuit |
| Patent Number: |
4,292,596 |
| Publication Date: |
September 29, 1981 |
| Appl. No: |
06/066,239 |
| Application Filed: |
August 13, 1979 |
| Abstract: |
A circuit for varying the gain of an amplifier circuit linearly in decibel by the use of a digital code signal varying linearly, wherein a resistance network to be connected between an amplifier having a fixed gain and an input or output portion for the amplification is connected and the gain of the amplifier as well as the values of resistance elements constituting the resistance network is set so that the transfer function of the amplifier circuit may become: ##EQU1## . |
| Inventors: |
Ishizuka, Kohei (Hachiouji, JPX); Kita, Yasuhiro (Hachiouji, JPX); Maeda, Narimichi (Tachikawt, JPX) |
| Assignees: |
Hitachi, Ltd. (Tokyo, JPX) |
| Claim: |
What is claimed is |
| Claim: |
1. A digital gain control circuit having (a) an input terminal and an output terminal; (b) an amplifier connected between said input and output terminals; and (c) a resistance network which includes a variable resistance circuit disposed between one of said terminals and said amplifier, said variable resistance circuit comprising a plurality of resistance elements and switch means including a plurality of switches for changing-over said resistance elements, said variable resistance circuit including circuit means for driving said plurality of switches directly with digital code signals, said amplifier and said resistance network being such that the transfer function between said input and output terminals is: ##EQU15## where Y denotes a constant which determines the gain of said amplifier and/or a value of the constituent resistance of said resistance network, G denotes a coefficient which varies in direct proportion to the digital code signal, and A and B denote constants. |
| Claim: |
2. A digital gain control circuit according to claim 1, wherein the constants A=-2 and B=1 |
| Claim: |
said resistance network comprises means for reversing the phase of an input signal applied to said input terminal and which feeds the opposite-phase signal forwards to the output of said amplifier, a fixed resistance connected between said input terminal and an input of said amplifier and which has a resistance value of (Y-1) R, and a variable resistance which is connected between said input of said amplifier and ground and which has a resistance value of R/G. |
| Claim: |
3. A digital gain control circuit according to claim 2, wherein said variable resistance comprises a plurality of series circuits consisting of resistance elements having resistance values (2.sup.n -1)/(2.sup.n-1-i)R(i=0, . . . and n-1) and switches SWi connected in parallel, and said switches SWi are controlled directly by bit signals of applied digital codes received from said circuit means. |
| Claim: |
4. A digital gain control circuit according to claim 3, wherein said amplifier is a differential amplifier, and |
| Claim: |
means for connecting a node between first and second resistances connected in series between said input terminal and ground and an end of a resistance with its other end connected to the output of said amplifier, and means for applying a voltage of said node between said first and second resistances to a minus input terminal of said differential amplifier. |
| Claim: |
5. A digital gain control circuit according to claim 1, wherein the constants A=-2 and B=1 |
| Claim: |
said resistance network comprises means for reversing the phase of an input signal applied to said input terminal and which feeds the opposite-phase signal forwards to an output of said amplifier, a variable resistance connected between said input terminal and an input of said amplifier and which has a variable resistance value of GR (R being a fixed resistance value), and a fixed resistance which is connected between said input of said amplifier and ground and which has a fixed resistance value of R/(Y-1). |
| Claim: |
6. A digital gain control circuit according to claim 5, wherein said variable resistance comprises a plurality of parallel circuits consisting of resistors having resistance values of (2.sup.n-1-i)/(2.sup.n-1)R(i=0, . . . and n-1) and switches SWi (n-1) connected in series, said switches SWi being controlled directly by bit signals of applied digital codes received from said circuit means. |
| Claim: |
7. A digital gain control circuit according to claim 1, wherein said resistance network comprises first, second, and third resistances connected in series between said input and output terminals, and a fourth resistance which is connected between said input and output terminals |
| Claim: |
said third resistance has a resistance value of (Y-1) R |
| Claim: |
said fourth resistance is a variable resistance which has a resistance value of R/G, said variable resistance being so constructed that series circuits consisting of resistance elements having resistance values of (2.sup.n -1)/(2.sup.n-1-i)R(i=0, . . . and n-1) and switches SWi are connected in parallel and that said switches SWi are controlled directly by bit signals of the digital codes, and |
| Claim: |
said amplifier has a potential of a node between said first and second resistances applied to a minus input terminal thereof, while an output terminal of said amplifier is connected to a node between said second and third resistors. |
| Claim: |
8. A digital gain control circuit according to claim 1, wherein said resistance network comprises first, second, and third resistances connected in series between said input and output terminals, and a resistance which is connected between said input and output terminals and which has a fixed resistance value of (Y-1) R |
| Claim: |
said third resistance is a variable resistance which has a resistance value of R/G, said variable resistance comprising a plurality of series circuits consisting of resistance elements having resistance values of (2.sup.n -1)/(2.sup.n-1-i).multidot.R(i=0, 1, . . . and (n-1)) and switches SWi connected in parallel and that said switches SWi are controlled directly by bit signals of applied digital codes received from said circuit means. |
| Claim: |
9. A digital gain control circuit according to claim 8, wherein said amplifier has a potential of a node between said first and second resistances applied to a minus input terminal thereof, while the output terminal of said amplifier is connected to a node between said second and third resistances. |
| Current U.S. Class: |
330/86; 330/254 |
| Current International Class: |
H03G 300 |
| Patent References Cited: |
3629720 December 1971 Sedra et al. |
| Other References: |
Sedra, et al. "Simple Digitally-Controlled Variable-Gain Linear D.C. Amplifier", Electronic Eng., Mar. 1969 pp. 362-365.
Ottesen et al. "Digitally Controlled Amplifier Circuits", IBM Tech. Discl. Bulletin, vol. 16, No. 11, Apr. pp. 3504-3505 74. |
| Primary Examiner: |
Smith, Alfred E. |
| Assistant Examiner: |
Grigsby, T. N. |
| Attorney, Agent or Firm: |
Craig and Antonelli |
| Accession Number: |
edspgr.04292596 |
| Database: |
USPTO Patent Grants |
