Bibliographic Details
| Title: |
DOUBLE-SIDED SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR THE SAME |
| Document Number: |
20120182692 |
| Publication Date: |
July 19, 2012 |
| Appl. No: |
13/346978 |
| Application Filed: |
January 10, 2012 |
| Abstract: |
A double-sided substrate includes a ceramic substrate, a first metal layer formed on one surface of the ceramic substrate and having a plurality of subsidiary metal layers which are laminated on the surface of the ceramic substrate and whose purities differ from each other and a second metal layer formed on the other surface of the ceramic substrate, wherein the closer to the ceramic substrate any subsidiary metal layer is located, the lower purity the subsidiary metal layer has. Additionally, a semiconductor includes the above double-sided substrate, a power element and a heat sink. |
| Inventors: |
MORI, Shogo (Aichi-ken, JP); IWATA, Yoshitaka (Aichi-ken, JP) |
| Assignees: |
KABUSHIKI KAISHA TOYOTA JIDOSHOKKI (Kariya-shi, JP) |
| Claim: |
1. A double-sided substrate comprising: a ceramic substrate; a first metal layer formed on one surface of the ceramic substrate and having a plurality of subsidiary metal layers which are laminated on the surface of the ceramic substrate and whose purities differ from each other; and a second metal layer formed on the other surface of the ceramic substrate, wherein the closer to the ceramic substrate any subsidiary metal layer is located, the lower purity the subsidiary metal layer has. |
| Claim: |
2. The double-sided substrate according to claim 1, wherein the higher purity any subsidiary metal layer has, the larger thickness the subsidiary metal layer has. |
| Claim: |
3. The double-sided substrate according to claim 1, wherein the subsidiary metal layer closer to the ceramic substrate is formed with thickness of 0.2-0.6 mm and the subsidiary metal layer far from the ceramic substrate is formed with thickness of 0.5-3.0 mm. |
| Claim: |
4. The double-sided substrate according to claim 1, wherein the subsidiary metal layer has a hole. |
| Claim: |
5. The double-sided substrate according to claim 1, wherein the subsidiary metal layers are made of aluminum, wherein the purity of aluminum of the subsidiary metal layer having the lowest purity among the subsidiary metal layers is 99.5 wt % or more, but less than 99.9 wt %, wherein the purity of aluminum of the subsidiary metal layer having the highest purity among the subsidiary metal layers is 99.99 wt % or more. |
| Claim: |
6. The double-sided substrate according to claim 1, wherein the first and the second metal layers are made of copper. |
| Claim: |
7. A semiconductor device, wherein the semiconductor device comprising: a double-sided substrate including: a ceramic substrate; a first metal layer formed on one surface of the ceramic substrate and having a plurality of subsidiary metal layers which are laminated on the surface and whose purities differ from each other, wherein the closer to the ceramic substrate any subsidiary metal layer is located, the lower purity the subsidiary metal layer has; and a second metal layer formed on the other surface of the ceramic substrate, a power element; and a heat sink. |
| Claim: |
8. The semiconductor device according to claim 7, wherein the heat sink is made of the same kind of material as the first and the second metal layers. |
| Claim: |
9. A method of manufacturing a semiconductor device including a ceramic substrate, a plurality of subsidiary metal layers forming a first metal layer, a second metal layer, a heat sink and a power element, wherein purities of the plurality of subsidiary metal layers differ from each other, wherein the closer to the ceramic substrate any subsidiary metal layer is located, the lower purity the subsidiary metal layer has, comprising the steps of: joining the ceramic substrate, the plurality of subsidiary metal layers forming the first metal layer, the second metal layer and the heat sink simultaneously by brazing in a first manufacturing process; and joining the power element to the second metal layer by soldering in a second manufacturing process. |
| Current U.S. Class: |
361/709 |
| Current International Class: |
05; 23; 23; 32; 32 |
| Accession Number: |
edspap.20120182692 |
| Database: |
USPTO Patent Applications |
