Bibliographic Details
| Title: |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| Document Number: |
20120153388 |
| Publication Date: |
June 21, 2012 |
| Appl. No: |
13/313620 |
| Application Filed: |
December 07, 2011 |
| Abstract: |
A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. |
| Inventors: |
SAYAMA, Hirokazu (Kanagawa, JP) |
| Claim: |
1. A semiconductor device having a high voltage p-channel transistor, the high voltage p-channel transistor comprising: a semiconductor substrate having a main surface and a p-type region therein: a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region located in a way to adjoin the p-type well region in a direction along the main surface, having a second p-type impurity region to obtain a source electrode; a gate electrode located between the first p-type impurity region and the second p-type impurity region in the direction along the main surface; and a p-type buried channel located over the n-type well region, extending along the main surface, wherein a border between the n-type well region and the p-type well region is located nearer to the first p-type impurity region than an end of the gate electrode near to the first p-type impurity region. |
| Claim: |
2. The semiconductor device according to claim 1, wherein the p-type buried channel is joined to the second p-type impurity region, and an end of the p-type buried channel near to the first p-type impurity region is located nearer to the first p-type impurity region than an end of the gate electrode end near to the first p-type impurity region. |
| Claim: |
3. The semiconductor device according to claim 1 or 2, wherein an insulating layer overlapping the gate electrode end near to the first p-type impurity region in a plan view and having a sufficient thickness to reach a deeper level than a bottom of the p-type buried channel is located in the main surface of the semiconductor substrate. |
| Claim: |
4. A semiconductor device having a high voltage p-channel transistor, the high voltage p-channel transistor comprising: a semiconductor substrate having a main surface and a p-type region therein: a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region located in a way to adjoin the p-type well region in a direction along the main surface, having a second p-type impurity region to obtain a source electrode; a gate electrode located between the first p-type impurity region and the second p-type impurity region in the direction along the main surface; and a p-type buried channel located over the n-type well region, extending along the main surface, wherein an insulating layer overlapping the gate electrode end near to the first p-type impurity region in a plan view and having a sufficient thickness to reach a deeper level than a bottom of the p-type buried channel is located in the main surface of the semiconductor substrate. |
| Claim: |
5. The semiconductor device according to claim 4, wherein a border between the n-type well region and the p-type well region is located nearer to the first p-type impurity region than the gate electrode gate near to the first p-type impurity region. |
| Claim: |
6. The semiconductor device according to claim 4 or 5, wherein the p-type buried channel is joined to the second p-type impurity region, and an end of the p-type buried channel near to the first p-type impurity region is located nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. |
| Claim: |
7. The semiconductor device according to any one of claims 1 to 6, further comprising a low voltage p-channel transistor located in parallel with the high voltage p-channel transistor in the direction along the main surface over the p-type region of the semiconductor substrate, wherein the high voltage p-channel transistor and the low voltage p-channel transistor share the p-type buried channel in the main surface. |
| Claim: |
8. A method for manufacturing a semiconductor device with a high voltage p-channel transistor, a process for forming the high voltage p-channel transistor comprising the steps of: preparing a semiconductor substrate having a main surface and a p-type region therein: forming, over the p-type region and in the main surface, a p-type well region having a first p-type impurity region to obtain a drain electrode; forming an n-type well region having a second p-type impurity region to obtain a source electrode in a way to adjoin the p-type well region in a direction along the main surface; forming a p-type buried channel located over the n-type well region, extending along the main surface; and forming a gate electrode between the first p-type impurity region and the second p-type impurity region in the direction along the main surface, wherein the step of forming the n-type well region and the step of forming the p-type buried channel are carried out using a mask temporally continuously, and wherein the n-type and p-type well regions are formed so that a border between the n-type well region and the p-type well region is located nearer to the first p-type impurity region than an end of the gate electrode near to the first p-type impurity region. |
| Claim: |
9. The semiconductor device manufacturing method according to claim 8, wherein the p-type buried channel is formed so as to be joined to the second p-type impurity region with an end of the p-type buried channel near to the first p-type impurity region located nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. |
| Claim: |
10. The semiconductor device manufacturing method according to claim 8 or 9, further comprising the step of forming an insulating layer overlapping the gate electrode end near to the first p-type impurity region in a plan view and having a sufficient thickness to reach a deeper level than a bottom of the p-type buried channel in the main surface of the semiconductor substrate. |
| Claim: |
11. A method for manufacturing a semiconductor device with a high voltage p-channel transistor, a process for forming the high voltage p-channel transistor comprising the steps of: preparing a semiconductor substrate having a main surface and a p-type region therein: forming, over the p-type region and in the main surface, a p-type well region having a first p-type impurity region to obtain a drain electrode; forming an n-type well region having a second p-type impurity region to obtain a source electrode in a way to adjoin the p-type well region in a direction along the main surface; forming a p-type buried channel located over the n-type well region, extending along the main surface; and forming a gate electrode between the first p-type impurity region and the second p-type impurity region in the direction along the main surface, wherein the step of forming the n-type well region and the step of forming the p-type buried channel are carried out using a mask temporally continuously, and the method further comprises a step of forming an insulating layer overlapping the gate electrode end near to the first p-type impurity region in a plan view and having a sufficient thickness to reach a deeper level than a bottom of the p-type buried channel in the main surface of the semiconductor substrate. |
| Claim: |
12. The semiconductor device manufacturing method according to claim 11, wherein a border between the n-type well region and the p-type well region is located nearer to the first p-type impurity region than an end of the gate electrode near to the first p-type impurity region. |
| Claim: |
13. The semiconductor device manufacturing method according to claim 11 or 12, wherein the p-type buried channel is formed so as to be joined to the second p-type impurity region with an end of the p-type buried channel near to the first p-type impurity region located nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. |
| Claim: |
14. The semiconductor device manufacturing method according to any one of claims 8 to 13, further comprising a step of forming a low voltage p-channel transistor located in parallel with the high voltage p-channel transistor in the direction along the main surface over the p-type region of the semiconductor substrate, wherein the high voltage p-channel transistor and the low voltage p-channel transistor are formed so as to share the p-type buried channel in the main surface. |
| Current U.S. Class: |
257/337 |
| Current International Class: |
01; 01; 01; 01 |
| Accession Number: |
edspap.20120153388 |
| Database: |
USPTO Patent Applications |
