| Title: |
POWER SAVINGS AND/OR DYNAMIC POWER MANAGEMENT IN A MEMORY |
| Document Number: |
20110296214 |
| Publication Date: |
December 1, 2011 |
| Appl. No: |
12/957569 |
| Application Filed: |
December 01, 2010 |
| Abstract: |
An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit. |
| Inventors: |
Arntzen, Eskild T. (Cheyenne, WY, US); Ellis, Jackson L. (Fort Collins, CO, US) |
| Claim: |
1. An apparatus comprising: a plurality of buffers each configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients; and a memory controller circuit configured to generate a clock enable signal in response to said plurality of access request signals, wherein said clock enable signal is configured to initiate entering and exiting a power savings mode of a memory circuit. |
| Claim: |
2. The apparatus according to claim 1, wherein said memory controller comprises: an arbiter circuit configured to generate (i) a transfer request signal in response to each of said access request signals and (ii) an alert signal in response to each of said access request signals. |
| Claim: |
3. The apparatus according to claim 2, wherein said alert signal is generated one or more clock cycles ahead of said transfer request signal. |
| Claim: |
4. The apparatus according to claim 2, wherein said memory controller further comprises: a protocol engine circuit configured to generate (i) a transfer protocol signal in response to said transfer requests and (ii) said clock enable signal in response to said alert signal. |
| Claim: |
5. The apparatus according to claim 2, wherein said alert signal is generated before said transfer request signal when said apparatus is operating in said power savings mode. |
| Claim: |
6. The apparatus according to claim 4, wherein said power savings mode is initiated when (i) said protocol engine circuit returns to an idle state and (ii) said memory circuit is precharged. |
| Claim: |
7. The apparatus according to claim 4, wherein said protocol engine circuit comprises a state machine configured to enter and exit said power savings mode. |
| Claim: |
8. The apparatus according to claim 4, wherein said transfer protocol signal is generated before said clock enable signal. |
| Claim: |
9. The apparatus according to claim 4, wherein said alert signal is generated before said transfer protocol signal. |
| Claim: |
10. The apparatus according to claim 1, wherein each of said access request signal is received directly from a respective one of said plurality of clients. |
| Claim: |
11. The apparatus according to claim 1, wherein said memory controller circuit ensures that said clock enable signal is asserted before a refresh command is presented to said memory. |
| Claim: |
12. The apparatus according to claim 1, wherein said memory controller circuit de-asserts said clock enable signal when said memory controller circuit is idle. |
| Claim: |
13. The apparatus according to claim 1, wherein said memory controller circuit exits said power savings mode to service said plurality of channel requests. |
| Claim: |
14. The apparatus according to claim 1, wherein said power savings mode is initiated when said plurality of channel requests are not received by said plurality of buffers for one or more clock cycles. |
| Claim: |
15. The apparatus according to claim 1, wherein said clock enable signal is (i) deasserted when entering said power savings mode of said memory circuit and (ii) asserted when exiting said power savings mode of said memory circuit. |
| Claim: |
16. The apparatus according to claim 1, wherein said apparatus is implemented as one or more integrated circuits. |
| Claim: |
17. A method for implementing power savings control in a memory comprising the steps of: (A) generating an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients; and (B) generating a clock enable signal in response to said plurality of access request signals, wherein said clock enable signal is configured to initiate entering and exiting a power savings mode of said memory. |
| Claim: |
18. An apparatus comprising: a memory controller circuit configured to generate a clock enable signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients; and a memory interface circuit configured to receive said clock enable signal, wherein said clock enable signal is configured to initiate entering and exiting a power savings mode of a memory circuit. |
| Current U.S. Class: |
713/320 |
| Current International Class: |
06; 06 |
| Accession Number: |
edspap.20110296214 |
| Database: |
USPTO Patent Applications |
