| Title: |
PARTITIONING MEMORY FOR ACCESS BY MULTIPLE REQUESTERS |
| Document Number: |
20110296124 |
| Publication Date: |
December 1, 2011 |
| Appl. No: |
12/899681 |
| Application Filed: |
October 07, 2010 |
| Abstract: |
An apparatus comprising a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources. The channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers. |
| Inventors: |
Fredenberg, Sheri L. (Windsor, CO, US); Ellis, Jackson L. (Fort Collins, CO, US); Arntzen, Eskild T. (Cheyenne, WY, US) |
| Claim: |
1. An apparatus comprising: a plurality of buffers each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients; and a channel router circuit configured to connect one or more of said buffers to one of a plurality of memory resources, wherein said channel router circuit returns a data signal to a respective one of said buffers in an order requested by each of said clients. |
| Claim: |
2. The apparatus according to claim 1, wherein each of said memory resources comprises (i) an arbiter, (ii) a protocol engine, and (iii) a memory device. |
| Claim: |
3. The apparatus according to claim 1, wherein each of said memory resources comprises: an arbiter circuit configured to receive each of a plurality of control signals; a protocol engine circuit configured to receive a selected one of said control signals; and a memory circuit configured to store and present said data signal in response to said selected control signal. |
| Claim: |
4. The apparatus according to claim 3, wherein each of said protocol engines presents and receives a respective one of said data signals from said channel router circuit. |
| Claim: |
5. The apparatus according to claim 3, wherein said memory circuits are implemented on an integrated circuit along with said plurality of buffers and said channel router circuit. |
| Claim: |
6. The apparatus according to claim 3, wherein said memory circuits are implemented on a separate integrated circuit from said plurality of buffers and said channel router circuit. |
| Claim: |
7. The apparatus according to claim 3, wherein said channel router circuit is configured to allow regioning of a physical layout. |
| Claim: |
8. The apparatus according to claim 3, wherein said memory circuits are interleaved by low address bits to increase memory bandwidth. |
| Claim: |
9. The apparatus according to claim 3, wherein each of said memory circuits is configured to share a common address space. |
| Claim: |
10. The apparatus according to claim 3, wherein one or more of said requestors operates at a first frequency that is different than a second frequency that one or more of said memory circuits operates. |
| Claim: |
11. The apparatus according to claim 1, wherein said channel router circuit allows each of said clients to simultaneously initiate access to one or more of said memory resources. |
| Claim: |
12. The apparatus according to claim 1, wherein said channel router allows independent arbitration of each of said memory resources. |
| Claim: |
13. The apparatus according to claim 1, wherein said channel router allows independent criteria to be used for arbitration of said memory resources. |
| Claim: |
14. The apparatus according to claim 1, wherein said apparatus allows parallel access by two or more of said clients of one or more of said memory resources. |
| Claim: |
15. The apparatus according to claim 1, wherein the number of said plurality of buffers may be scaled to accommodate a particular number of clients. |
| Claim: |
16. The apparatus according to claim 1, wherein the plurality of said buffers are implemented for each of said plurality of clients. |
| Claim: |
17. The apparatus according to claim 1, wherein said buffers each comprise first-in, first-out FIFO buffers. |
| Claim: |
18. The apparatus according to claim 1, wherein said memory resources comprise at least one of (i) a Dynamic Random Access Memory (DRAM), (ii) a Synchronous Random Access Memory (SRAM), (iii) a DDR memory, (iv) a RDRAM memory, (v) a flash memory, (vi) a non-volatile memory, (vii) a volatile memory and (viii) other type of available memory. |
| Claim: |
19. The apparatus according to claim 1, wherein said apparatus is implemented as an integrated circuit. |
| Claim: |
20. A method for partitioning a memory for access by a plurality of requestors comprising the steps of: (A) generating a control signal in a buffer in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients; and (B) connecting one or more of said buffers to one of a plurality of memory resources, wherein step (B) returns a data signal to a respective one of said buffers in an order requested by each of said clients. |
| Current U.S. Class: |
711/157 |
| Current International Class: |
06; 06; 06 |
| Accession Number: |
edspap.20110296124 |
| Database: |
USPTO Patent Applications |
