Bibliographic Details
| Title: |
VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR |
| Document Number: |
20110231593 |
| Publication Date: |
September 22, 2011 |
| Appl. No: |
12/958298 |
| Application Filed: |
December 01, 2010 |
| Abstract: |
An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. |
| Inventors: |
YASUFUKU, Kenta (Kanagawa, JP); IWASA, Shigeaki (Kanagawa, JP); KUROSAWA, Yasuhiko (Kanagawa, JP); HAYASHI, Hiroo (Kanagawa, JP); MAEDA, Seiji (Kanagawa, JP); SAITO, Mitsuo (Kanagawa, JP) |
| Assignees: |
KABUSHIKI KAISHA TOSHIBA (Tokyo, JP) |
| Claim: |
1. A virtual address cache memory comprising: a Translation Lookaside Buffer (TLB) virtual page memory configured to hold entry data comprising a virtual page tag, the virtual page tag being a predetermined high-order bit (most significant bit side) of a virtual address for a process, to output a hit signal when the virtual page tag corresponds to a virtual page tag from a processor, and to rewrite the entry data when a rewrite to a TLB occurs; a data memory configured to hold cache data using the virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to hold a physical address corresponding to the virtual address held in the TLB virtual page memory, and to rewrite the held physical address when the rewrite to the TLB occurs; and a second physical address memory configured to hold a physical address for the cache data held in the data memory, and to rewrite the held physical address when the cache data is written to the data memory after the occurrence of the rewrite to the TLB. |
| Claim: |
2. The virtual address cache memory of claim 1, wherein the physical address rewritten in the second physical address memory is a physical address corresponding to a virtual address invalidated as a result of the rewrite to the TLB upon occurrence of a TLB miss. |
| Claim: |
3. The virtual address cache memory of claim 2, wherein the second physical address memory is configured to rewrite the corresponding physical address to a physical address obtained as a result of cache refilling after the occurrence of the rewrite to the TLB. |
| Claim: |
4. The virtual address cache memory of claim 2, wherein the cache state memory is configured to set a predetermined flag upon the occurrence of the rewrite to the TLB; and wherein the second physical address memory is configured to rewrite the physical address when the predetermined flag is set in the cache state memory. |
| Claim: |
5. The virtual address cache memory of claim 4, wherein the predetermined flag is reset when the corresponding physical address is rewritten. |
| Claim: |
6. A multiprocessor comprising: processors connected via a bus, each processor comprising a central processing unit (CPU), a cache memory and a direct memory access (DMA) controller; and a memory controller connected to the bus, the memory controller being a control section for a main memory, wherein the cache memory comprises: a TLB virtual page memory configured to hold entry data comprising a virtual page tag, the virtual page tag being a predetermined high-order bit (most significant bit side) of a virtual address for a process, to output a hit signal when the virtual page tag corresponds to a virtual page tag from a processor, and to rewrite the entry data when a TLB miss occurs; a data memory configured to hold cache data using the virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to hold a physical address corresponding to the virtual address held in the TLB virtual page memory, and to rewrite the held physical address when the TLB miss occurs; and a second physical address memory configured to hold a physical address for the cache data held in the data memory, and to rewrite the held physical address when the TLB miss occurs, and wherein the CPU is configured to set a transfer source address and a transfer destination address in the DMA transfer, using virtual addresses, when data is transferred by DMA transfer using the DMA controller from the main memory to the cache memory. |
| Claim: |
7. The multiprocessor of claim 6, wherein, when the data is written to the transfer destination address, the cache memory is configured to write Dirty to an entry in the cache state memory, the entry corresponding to an area in which the data has been written. |
| Claim: |
8. The multiprocessor of claim 7, wherein the DMA controller is configured to perform the DMA transfer on the basis of a cache line in the cache memory. |
| Claim: |
9. The multiprocessor of claim 7, wherein the transfer destination address is the same as the transfer source address. |
| Claim: |
10. The multiprocessor of claim 6, Wherein, when the TLB miss or a cache miss occurs for the transfer source address, the cache memory is configured to read target data from a physical address corresponding to the transfer source address, the transfer source address being the virtual address, and to write the target data to a physical address corresponding to the transfer destination address in the main memory, without performing TLB miss processing or cache miss processing. |
| Claim: |
11. The multiprocessor of claim 10, wherein the DMA controller is configured to perform the DMA transfer on the basis of a cache line in the cache memory. |
| Claim: |
12. A processor comprising: a CPU; a primary cache memory; and a secondary, tertiary or more-order cache memory, wherein the secondary or tertiary or more-order cache memory comprises: a TLB virtual page memory configured to hold entry data comprising a virtual page tag, the virtual page tag being a predetermined high-order bit (most significant bit side) of a virtual address for a process, and to output a hit signal when the virtual page tag corresponds to a virtual page tag from a processor; a data memory configured to hold cache data using the virtual page tag or a page offset as a cache index; and a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index. |
| Claim: |
13. The processor of claim 12, wherein the data memory is configured to perform replacement of the cache data on the basis of a virtual page for an operating system managing execution of the process. |
| Claim: |
14. The processor of claim 12, wherein cache state management by the cache state memory is performed on the basis of a cash block of the data memory that is smaller than a page size. |
| Claim: |
15. The processor of claim 12, further comprising a snoop mechanism for maintaining coherency of the cash data in the data memory. |
| Claim: |
16. The processor of claim 12, wherein an identification number comprising a process identifier other than a virtual address is also a comparison object in addition to the virtual address. |
| Claim: |
17. The processor of claim 12, further comprising a mechanism configured to hold a physical address for the cache data held in the data memory, and check whether data for the physical address is held in the data memory. |
| Claim: |
18. The processor of claim 17, wherein the same physical address is configured to be registered in a plurality of entries. |
| Current U.S. Class: |
711/3 |
| Current International Class: |
06; 06; 06 |
| Accession Number: |
edspap.20110231593 |
| Database: |
USPTO Patent Applications |
