Bibliographic Details
| Title: |
MEMORY |
| Document Number: |
20100008164 |
| Publication Date: |
January 14, 2010 |
| Appl. No: |
12/562724 |
| Application Filed: |
September 18, 2009 |
| Abstract: |
A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor. |
| Inventors: |
Murayama, Yoshiki (Anpachi-gun, JP); Yamada, Kouichi (Hashima-gun, JP) |
| Claim: |
1. An apparatus, comprising: a memory cell coupled to a bit line and configured to hold data, wherein the data includes first data or second data; a first transistor configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read; and a second transistor configured to feed different quantities of currents towards the first transistor, in response to reading the first data or the second data, by changing a potential difference between a first terminal of the second transistor and either a second terminal or a third terminal of the second transistor, wherein the potential difference is changed in response to different potentials generated on a terminal of the first transistor if the first data or the second data is read. |
| Claim: |
2. The apparatus of claim 1, wherein the first transistor comprises a bipolar transistor, and wherein the second transistor comprises a field-effect transistor. |
| Claim: |
3. The apparatus of claim 1, wherein the memory cell comprises a ferroelectric memory cell. |
| Claim: |
4. The apparatus of claim 1, wherein the memory cell comprises a phase-change memory cell. |
| Claim: |
5. The apparatus of claim 1, wherein the memory cell comprises a resistance-change memory cell. |
| Claim: |
6. An apparatus, comprising: a memory cell coupled to a bit line and configured to hold data; and a first transistor having a first terminal coupled to the bit line, wherein the first transistor is configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read; wherein a second terminal of the first transistor is coupled to a first end of a second transistor, and wherein a second end of the second transistor is coupled to a sense amplifier. |
| Claim: |
7. The apparatus of claim 6, further comprising a resistor having a resistance larger than an interconnection resistance and having a first end coupled to the second terminal of the first transistor, wherein a second end of the resistor is configured to receive a positive potential while a negative potential is applied to a third terminal of the first transistor. |
| Claim: |
8. The apparatus of claim 6, wherein the first transistor comprises a bipolar transistor, and wherein the second transistor comprises a field-effect transistor. |
| Claim: |
9. The apparatus of claim 6, wherein the memory cell comprises a ferroelectric memory cell. |
| Claim: |
10. The apparatus of claim 6, wherein the memory cell comprises a phase-change memory cell. |
| Claim: |
11. The apparatus of claim 6, wherein the memory cell comprises a resistance-change memory cell. |
| Claim: |
12. An apparatus, comprising: a memory cell coupled to a bit line and configured to hold data, wherein the data includes first data or second data; and an amplification circuit coupled to the bit line and configured to receive and amplify an input current corresponding to the data that appears on the bit line if the data held in the memory cell is read, wherein the amplification circuit is further configured to generate an output current having a first magnitude if the first data is read or a second magnitude if the second data is read. |
| Claim: |
13. The apparatus of claim 12, wherein the amplification circuit comprises a transistor having a first terminal coupled to the bit line and configured to receive the input current and a second terminal configured to provide the output current. |
| Claim: |
14. The apparatus of claim 13, wherein the transistor comprises a bipolar transistor, the first terminal comprises a base of the bipolar transistor, and the second terminal comprises a collector of the bipolar transistor. |
| Claim: |
15. The apparatus of claim 13, wherein a difference between the first and second magnitudes is greater than a difference between currents appearing on the bit line if reading the first data or the second data. |
| Claim: |
16. The apparatus of claim 13, wherein the memory cell comprises a ferroelectric memory cell. |
| Claim: |
17. The apparatus of claim 13, wherein the memory cell comprises a phase-change memory cell. |
| Claim: |
18. The apparatus of claim 13, wherein the memory cell comprises a resistance-change memory cell. |
| Claim: |
19. The apparatus of claim 13, wherein the memory cell comprises a memory cell of a random access memory (RAM). |
| Current U.S. Class: |
365189/011 |
| Current International Class: |
11; 11; 11 |
| Accession Number: |
edspap.20100008164 |
| Database: |
USPTO Patent Applications |
