| Title: |
Multidimensional Process Corner Derivation Using Surrogate Based Simultaneous Yield Analysis |
| Document Number: |
20080195359 |
| Publication Date: |
August 14, 2008 |
| Appl. No: |
11/674572 |
| Application Filed: |
February 13, 2007 |
| Abstract: |
A system and method for deriving semiconductor manufacturing process corners using surrogate simulations is disclosed. The method may be used to determine individual performance metric yields, the number of out-of-specification conditions for a given number of simulation samples, and a total yield prediction for simultaneous multi-variable conditions. A surrogate simulation model, such as a Response Surface Model, may be generated from circuit simulation data or parametric data measurements and may be executed using a large number of multi-variable sample points to determine process corners defining yield limits for a device. The model may also be used to simulate process shifts and exaggerated input ranges for critical device parameters. In some embodiments, the derived process corners may better represent physically possible worst-case process corners than traditional general-purpose process corners, and may address differences in process sensitivities for individual circuits of the device. |
| Inventors: |
Barker, Aaron J. (Broomfield, CO, US); Russell, Edmund L. (Danville, CA, US) |
| Claim: |
1. A method comprising: identifying two or more device parameters of a semiconductor device; defining specification limits for one or more performance measures of the semiconductor device; determining a distribution of each of the one or more performance measures dependent on each of the two or more device parameters; generating a surrogate simulation model dependent on results of said determining; simulating behavior of the semiconductor device using the surrogate simulation model; identifying one or more candidate process corners dependent on results of said simulating, wherein a candidate process corner defines a combination of values for two or more of the two or more device parameters for which said results of said simulating indicate that pre-determined criteria for one or more of the one or more performance measures are met. |
| Claim: |
2. The method of claim 1, further comprising estimating a manufacturing yield of the semiconductor device by simulating the semiconductor device at one of the one or more candidate process corners. |
| Claim: |
3. The method of claim 1, further comprising sorting the one or more candidate process corners according to their respective root sum square values to identify a pre-determined number of candidate process corners nearest to a process center. |
| Claim: |
4. The method of claim 1, further comprising determining that two or more of the two or more device parameters exhibit a positive correlation, a negative correlation, or no correlation with respect to the one or more performance measures. |
| Claim: |
5. The method of claim 1, further comprising verifying applicability of each of the one or more candidate process corners by repeating said determining a distribution of each of the one or more performance measures using the values of each of the two or more device parameters defined by each of the candidate process corners. |
| Claim: |
6. The method of claim 1, further comprising simulating a manufacturing process shift using the surrogate model by replacing the determined distribution with a modified distribution representing the manufacturing process shift in a surrogate model simulation instance. |
| Claim: |
7. The method of claim 1, wherein the surrogate model comprises a Response Surface Model (RSM). |
| Claim: |
8. The method of claim 1, wherein said simulating behavior of the semiconductor device using the surrogate simulation model comprises simulating the behavior of the semiconductor device using a larger input data set than an input data set used in said determining a distribution of each of the one or more performance measures dependent on each of the two or more device parameters. |
| Claim: |
9. The method of claim 1, further comprising refining said surrogate model by discarding terms corresponding to device parameter value combinations that are not correlated to the one or more performance measures or are not physically likely to occur. |
| Claim: |
10. The method of claim 1, wherein said determining a distribution comprises, for each given one of the two or more device parameters, simulating the semiconductor device while varying the given one of the two or more device parameters and not varying any other device parameters. |
| Claim: |
11. The method of claim 1, wherein said determining a distribution comprises accessing performance measurement data collected from an instance of the semiconductor device during testing. |
| Claim: |
12. A computer-readable storage medium comprising program instructions computer-executable to implement: identifying two or more device parameters of a semiconductor device; defining specification limits for one or more performance measures of the semiconductor device; determining a distribution of each of the one or more performance measures dependent on each of the two or more device parameters; generating a surrogate simulation model dependent on results of said determining; simulating behavior of the semiconductor device using the surrogate simulation model; identifying one or more candidate process corners dependent on results of said simulating, wherein a candidate process corner defines a combination of values for two or more of the two or more device parameters for which said results of said simulating indicate that pre-determined criteria for one or more of the one or more performance measures are met. |
| Claim: |
13. The storage medium of claim 12, further comprising program instructions computer-executable to implement estimating a manufacturing yield of the semiconductor device by simulating the semiconductor device at one of the one or more candidate process corners. |
| Claim: |
14. The storage medium of claim 12, further comprising program instructions computer-executable to implement sorting the one or more candidate process corners according to their respective root sum square values to identify a pre-determined number of candidate process corners nearest to a process center. |
| Claim: |
15. The storage medium of claim 12, further comprising program instructions computer-executable to implement determining that two or more of the two or more device parameters exhibit a positive correlation, a negative correlation, or no correlation with respect to the one or more performance measures. |
| Claim: |
16. The storage medium of claim 12, further comprising program instructions computer-executable to implement simulating a manufacturing process shift using the surrogate model by replacing the determined distribution with a modified distribution representing the manufacturing process shift in a surrogate model simulation instance. |
| Claim: |
17. A system, comprising: a processor; and a memory, wherein the memory comprises program instructions executable by the processor to: identify two or more device parameters of a semiconductor device; define specification limits for one or more performance measures of the semiconductor device; determine a distribution of each of the one or more performance measures dependent on each of the two or more device parameters; generate a surrogate simulation model dependent on results of said determining; simulate behavior of the semiconductor device using the surrogate simulation model; identify one or more candidate process corners dependent on results of said simulating, wherein a candidate process corner defines a combination of values for two or more of the two or more device parameters for which said results of said simulating indicate that pre-determined criteria for one or more of the one or more performance measures are met. |
| Claim: |
18. The system of claim 17, wherein the memory further comprises program instructions executable by the processor to estimate a manufacturing yield of the semiconductor device by simulating the semiconductor device at one of the one or more candidate process corners. |
| Claim: |
19. The system of claim 17, wherein the memory further comprises program instructions executable by the processor to sort the one or more candidate process corners according to their respective root sum square values to identify a pre-determined number of candidate process corners nearest to a process center. |
| Claim: |
20. The system of claim 17, wherein the memory further comprises program instructions executable by the processor to simulate a manufacturing process shift using the surrogate model by replacing the determined distribution with a modified distribution representing the manufacturing process shift in a surrogate model simulation instance. |
| Current U.S. Class: |
703/2 |
| Current International Class: |
06; 06; 06 |
| Accession Number: |
edspap.20080195359 |
| Database: |
USPTO Patent Applications |
