| Title: |
Semiconductor device manufacturing method |
| Document Number: |
20070087559 |
| Publication Date: |
April 19, 2007 |
| Appl. No: |
11/639296 |
| Application Filed: |
December 15, 2006 |
| Abstract: |
A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on a substrate and impurity ions are implanted into the surface of the substrate to form source/drain regions (diffusion layers: 1A, 1B) on both sides of the gate electrode. Also, impurity ions are implanted to control the resistance value of the resistive interconnection. Next, a sidewall film is formed to cover the resistive interconnection. Then a heat treatment is performed to activate the source/drain regions (diffusion layers: 1A, 1B). |
| Inventors: |
Iizuka, Koji (Tokyo, JP) |
| Assignees: |
RENESAS TECHNOLOGY CORP. (Tokyo, JP) |
| Claim: |
1-13. (canceled) |
| Claim: |
14. A semiconductor device manufacturing method comprising the steps of: (a) forming a poly-silicon on a substrate and on an element isolation region; (b) etching said poly-silicon to form a resistive interconnection on said element isolation region and a gate electrode on said substrate; (c) implanting impurity ions into a surface of said substrate to form a diffusion layer; (d) forming an insulating film to cover said resistive interconnection and said gate electrode; and (e) heating said substrate to activate said diffusion layer, after said step (c), wherein said step (c) include the step of forming a nitride film to cover said resistive interconnection. |
| Claim: |
15. The semiconductor device manufacturing method according to claim 14, further comprising, before said step (d), the steps of: (f) forming sidewall films on side surfaces of said gate electrode; and (g) after said step (f), implanting impurity ions into said substrate on both sides of gate electrode and into said resistive interconnection to form said diffusion layer and to control a resistance value of said resistive interconnection. |
| Claim: |
16. The semiconductor device manufacturing method according to claim 14, further comprising, after said step (d), the steps of: (h) forming on opening in said insulating film, said opening reaching said resistive interconnection. |
| Claim: |
17. The semiconductor device manufacturing method according to claim 16, further comprising, after said step (h), the steps of: (i) forming an interlayer insulating film covering said resistive interconnection and said gate electrode; and (j) forming a first contact hole extending from the upper surface of said interlayer insulating film to reach said gate electrode and forming a second contact hole extending from the upper surface of said interlayer insulating film through said opening to reach said resistive interconnection. |
| Claim: |
18. The semiconductor device manufacturing method according to claim 16, further comprising, after said step (h), the steps of: (k) applying a process of lower the resistance of said resistive interconnection in a region exposed in said opening. |
| Current U.S. Class: |
438622/000 |
| Current International Class: |
01 |
| Accession Number: |
edspap.20070087559 |
| Database: |
USPTO Patent Applications |
