Bibliographic Details
| Title: |
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips |
| Authors: |
Si, X., Tu, Y.-N., Huang, W.-H., Su, J.-W., Lu, P.-J., Wang, J.-H., Liu, T.-W., Wu, S.-Y., Liu, R., Chou, Y.-C., Zhang, Z., Sie, S.-H., Wei, W.-C., Lo, Y.-C., Wen, T.-H., Hsu, T.-H., Chen, Y.-K., Shih, W., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., Lien, N.-C., Shih, W.-C., He, Y., Li, Q., Chang, M.-F. |
| Source: |
2020 IEEE International Solid-State Circuits Conference - (ISSCC) Solid-State Circuits Conference - (ISSCC), 2020 IEEE International. :246-248 Feb, 2020 |
| Relation: |
2020 IEEE International Solid-State Circuits Conference - (ISSCC) |
| Database: |
IEEE Xplore Digital Library |
