Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors
| Title: | Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors |
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| Authors: | Lee, Jen-Hao, Chen, Eliot S.H., Lee, Yung-Huei, Lin, Chun-Hung, Wu, Chun-Yu, Hsieh, Ming-Han, Huang, Kevin, Wang, Jhong-Sheng, Tsai, Yung-Sheng, Lu, Ryan, Shih, Jiaw-Ren |
| Source: | 2015 IEEE International Integrated Reliability Workshop (IIRW) Integrated Reliability Workshop (IIRW), 2015 IEEE International. :63-67 Oct, 2015 |
| Relation: | 2015 IEEE International Integrated Reliability Workshop (IIRW) |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9781467373951 9781467373944 9781467373968 |
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| ISSN: | 23748036 |
| DOI: | 10.1109/IIRW.2015.7437068 |
| Published in: | 2015 IEEE International Integrated Reliability Workshop (IIRW), Integrated Reliability Workshop (IIRW), 2015 IEEE International |