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Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing

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Title: Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing
Authors: Shaik, S., Sri Rama Krishna, K., Vaddi, R.
Source: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 29th International Conference on. :306-311 Jan, 2016
Relation: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)
Database: IEEE Xplore Digital Library
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  Data: Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing
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  Data: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 29th International Conference on. :306-311 Jan, 2016
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/VLSID.2016.100
    PhysicalDescription:
      Pagination:
        PageCount: 6
        StartPage: 306
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      – TitleFull: Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing
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      – PersonEntity:
          Name:
            NameFull: Shaik, S.
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          Name:
            NameFull: Sri Rama Krishna, K.
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            NameFull: Vaddi, R.
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          Dates:
            – D: 01
              M: 01
              Type: published
              Y: 2016
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