Bibliographic Details
| Title: |
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing |
| Authors: |
Shaik, S., Sri Rama Krishna, K., Vaddi, R. |
| Source: |
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 29th International Conference on. :306-311 Jan, 2016 |
| Relation: |
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) |
| Database: |
IEEE Xplore Digital Library |
