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Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme

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Title: Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme
Authors: Chang, Meng-Fan, Kuo, Chia-Cheng, Sheu, Shyh-Shyuan, Lin, Chorng-Jung, King, Ya-Chin, Lin, Zhe-Hui, Su, Keng-Li, Chen, Yu-Sheng, Lin, Wen-Pin, Lee, Heng-Yuan, Tsai, Chen-Han, Chen, Wei-Su, Chen, Frederick T., Ku, Tzu-Kun, Kao, Ming-Jer, Tsai, Ming-Jinn, Wu, Jui-Jen, Chih, Yu-Der, Natarajan, Sreedhar
Source: 2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :C112-C113 Jun, 2013
Relation: 2013 Symposium on VLSI Technology
Database: IEEE Xplore Digital Library
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  Data: Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme
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  Data: 2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :C112-C113 Jun, 2013
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  Data: 2013 Symposium on VLSI Technology
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      – TitleFull: Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme
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