Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme
| Title: | Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme |
|---|---|
| Authors: | Chang, Meng-Fan, Kuo, Chia-Cheng, Sheu, Shyh-Shyuan, Lin, Chorng-Jung, King, Ya-Chin, Lin, Zhe-Hui, Su, Keng-Li, Chen, Yu-Sheng, Lin, Wen-Pin, Lee, Heng-Yuan, Tsai, Chen-Han, Chen, Wei-Su, Chen, Frederick T., Ku, Tzu-Kun, Kao, Ming-Jer, Tsai, Ming-Jinn, Wu, Jui-Jen, Chih, Yu-Der, Natarajan, Sreedhar |
| Source: | 2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :C112-C113 Jun, 2013 |
| Relation: | 2013 Symposium on VLSI Technology |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9781467352260 9784863483477 |
|---|---|
| ISSN: | 07431562 21589682 |
| Published in: | 2013 Symposium on VLSI Technology, VLSI Technology (VLSIT), 2013 Symposium on |