Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
| Title: | Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits |
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| Authors: | Tsai, H.-W., Ker, M.-D. |
| Source: | IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 14(1):493-498 Mar, 2014 |
| Database: | IEEE Xplore Digital Library |
| ISSN: | 15304388 15582574 |
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| DOI: | 10.1109/TDMR.2012.2206391 |
| Published in: | IEEE Transactions on Device and Materials Reliability, Device and Materials Reliability, IEEE Transactions on, IEEE Trans. Device Mater. Relib. |