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An efficient architecture of bitplane coding in VC-1 for real-time video processing

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Title: An efficient architecture of bitplane coding in VC-1 for real-time video processing
Authors: Lim, Y.-H., Jun, S.-S., Kang, J.-S.
Source: 2007 IEEE International Symposium on Signal Processing and Information Technology Signal Processing and Information Technology, 2007 IEEE International Symposium on. :1198-1203 Dec, 2007
Relation: 2007 IEEE International Symposium on Signal Processing and Information Technology
Database: IEEE Xplore Digital Library
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  Data: 2007 IEEE International Symposium on Signal Processing and Information Technology Signal Processing and Information Technology, 2007 IEEE International Symposium on. :1198-1203 Dec, 2007
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  Data: 2007 IEEE International Symposium on Signal Processing and Information Technology
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      – Type: doi
        Value: 10.1109/ISSPIT.2007.4458061
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        StartPage: 1198
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      – TitleFull: An efficient architecture of bitplane coding in VC-1 for real-time video processing
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            NameFull: Lim, Y.-H.
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            NameFull: Jun, S.-S.
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            NameFull: Kang, J.-S.
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              Type: published
              Y: 2007
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            – TitleFull: 2007 IEEE International Symposium on Signal Processing and Information Technology, Signal Processing and Information Technology, 2007 IEEE International Symposium on
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