A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell
| Title: | A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell |
|---|---|
| Authors: | Cheng, Kuan-Lun, Wu, C. C., Wang, Y. P., Lin, D. W., Chu, C. M., Tarng, Y. Y., Lu, S. Y., Yang, S. J., Hsieh, M. H., Liu, C. M., Fu, S. P., Chen, J. H., Lin, C. T., Lien, W. Y., Huang, H. Y., Wang, P. W., Lin, H. H., Lee, D. Y., Huang, M. J., Nieh, C. F., Lin, L. T., Chen, C. C., Chang, W., Chiu, Y. H., Wang, M. Y., Yeh, C. H., Chen, F. C., Wu, C. M., Chang, Y. H., Wang, S. C., Hsieh, H. C., Lei, M. D., Goto, K., Tao, H. J., Cao, M., Tuan, H. C., Diaz, C. H., Mii, Y. J. |
| Source: | 2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :243-246 Dec, 2007 |
| Relation: | 2007 IEEE International Electron Devices Meeting |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9781424415076 9781424415083 |
|---|---|
| ISSN: | 01631918 2156017X |
| DOI: | 10.1109/IEDM.2007.4418913 |
| Published in: | 2007 IEEE International Electron Devices Meeting, Electron Devices Meeting, 2007. IEDM 2007. IEEE International |