Conference
Test time reduction reusing multiple processors in a network-on-chip based architecture
| Title: | Test time reduction reusing multiple processors in a network-on-chip based architecture |
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| Authors: | Amory, A.M., Lubaszewski, M., Moraes, F.G., Moren, E.I. |
| Source: | Design, Automation and Test in Europe Design, Automation and Test in Europe, 2005. Proceedings. :62-63 Vol. 1 2005 |
| Relation: | Proceedings. Design, Automation and Test in Europe |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 0769522882 9780769522883 |
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| ISSN: | 15301591 15581101 |
| DOI: | 10.1109/DATE.2005.304 |
| Published in: | Design, Automation and Test in Europe, Design, Automation and Test in Europe, 2005. Proceedings |