Bibliographic Details
| Title: |
30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681\mu\mathrm{m}$ 1T-1MTJ Cross-Point Cell |
| Authors: |
Hatsuda, Kosuke, Hoya, Katsuhiko, Takizawa, Ryousuke, Matsuoka, Fumiyoshi, Yasuda, Takaya, Katayama, Akira, Miyakawa, Tadashi, Senju, Kazuyo, Okawa, Kazuki, Furukawa, Yuka, Shimada, Yu, Kotake, Katsuya, Hirokawa, Sayaka, Shin, Min Chul, Kim, Dong Keun, Kim, Tae Ho, Kim, Kyunghoon, Aikawa, Hisanori, Song, Jeonghwan, Nagase, Toshihiko, Seo, Soo Man, Kim, Soo Gil, Cha, Seon Yong |
| Source: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:1-3 Feb, 2025 |
| Relation: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |
