Bibliographic Details
| Title: |
24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW |
| Authors: |
Zhong, Junlin, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi-Hang |
| Source: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:432-434 Feb, 2025 |
| Relation: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |
