| Title: |
19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving $57.9\mathbf{fs}_{\text{rms}}$ Jitter, −249.7dB FoM, and $\mathbf{1.98\mu} \mathbf{S}$ Locking Time Using Polarity-Reversible SSPD |
| Authors: |
Li, Haoran, Li, Jinge, Jiang, Xueying, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui-In |
| Source: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:1-3 Feb, 2025 |
| Relation: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |
