DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

Bibliographic Details
Title: DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET
Authors: Gao, Fei, Chang, Ting-Jung, Li, Ang, Orenes-Vera, Marcelo, Giri, Davide, Jackson, Paul J., Ning, August, Tziantzioulis, Georgios, Zuckerman, Joseph, Tu, Jinzheng, Xu, Kaifeng, Chirkov, Grigory, Tombesi, Gabriele, Balkind, Jonathan, Martonosi, Margaret, Carloni, Luca, Wentzlaff, David
Source: 2023 IEEE Custom Integrated Circuits Conference (CICC) Custom Integrated Circuits Conference (CICC), 2023 IEEE. :1-2 Apr, 2023
Relation: 2023 IEEE Custom Integrated Circuits Conference (CICC)
Database: IEEE Xplore Digital Library