Bibliographic Details
| Title: |
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators |
| Authors: |
Ferry, Corentin, Derumigny, Nicolas, Derrien, Steven, Rajopadhye, Sanjay |
| Publication Year: |
2024 |
| Collection: |
Computer Science |
| Subject Terms: |
Computer Science - Hardware Architecture |
| More Details: |
Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve the efficiency of transfers. This paper addresses the later issue by proposing (i) a compiler-based approach to accelerator's data layout to maximize contiguous access to off-chip memory, and (ii) data packing and runtime compression techniques that take advantage of this layout to further improve memory performance. We show that our approach can decrease the I/O cycles up to $7\times$ compared to un-optimized memory accesses.
Comment: 11 pages, 11 figures, 2 tables |
| Document Type: |
Working Paper |
| Access URL: |
http://arxiv.org/abs/2401.12071 |
| Accession Number: |
edsarx.2401.12071 |
| Database: |
arXiv |
