Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout
| Title: | Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout |
|---|---|
| Authors: | Ferry, Corentin, Yuki, Tomofumi, Derrien, Steven, Rajopadhye, Sanjay |
| Publication Year: | 2022 |
| Collection: | Computer Science |
| Subject Terms: | Computer Science - Hardware Architecture, B.4.4 |
| More Details: | Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator's effective performance. Techniques enabling data reuse, such as tiling, lower the pressure on memory traffic but still often leave the accelerators I/O-bound. A further increase in effective bandwidth is possible by using burst rather than element-wise accesses, provided the data is contiguous in memory. In this paper, we propose a memory allocation technique, and provide a proof-of-concept source-to-source compiler pass, that enables such burst transfers by modifying the data layout in external memory. We assess how this technique pushes up the memory throughput, leaving room for exploiting additional parallelism, for a minimal logic overhead. Comment: 16 pages; 17 figures |
| Document Type: | Working Paper |
| Access URL: | http://arxiv.org/abs/2202.05933 |
| Accession Number: | edsarx.2202.05933 |
| Database: | arXiv |
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| Items | – Name: Title Label: Title Group: Ti Data: Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ferry%2C+Corentin%22">Ferry, Corentin</searchLink><br /><searchLink fieldCode="AR" term="%22Yuki%2C+Tomofumi%22">Yuki, Tomofumi</searchLink><br /><searchLink fieldCode="AR" term="%22Derrien%2C+Steven%22">Derrien, Steven</searchLink><br /><searchLink fieldCode="AR" term="%22Rajopadhye%2C+Sanjay%22">Rajopadhye, Sanjay</searchLink> – Name: DatePubCY Label: Publication Year Group: Date Data: 2022 – Name: Subset Label: Collection Group: HoldingsInfo Data: Computer Science – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+Science+-+Hardware+Architecture%22">Computer Science - Hardware Architecture</searchLink><br /><searchLink fieldCode="DE" term="%22B%2E4%2E4%22">B.4.4</searchLink> – Name: Abstract Label: Description Group: Ab Data: Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator's effective performance. Techniques enabling data reuse, such as tiling, lower the pressure on memory traffic but still often leave the accelerators I/O-bound. A further increase in effective bandwidth is possible by using burst rather than element-wise accesses, provided the data is contiguous in memory. In this paper, we propose a memory allocation technique, and provide a proof-of-concept source-to-source compiler pass, that enables such burst transfers by modifying the data layout in external memory. We assess how this technique pushes up the memory throughput, leaving room for exploiting additional parallelism, for a minimal logic overhead.<br />Comment: 16 pages; 17 figures – Name: TypeDocument Label: Document Type Group: TypDoc Data: Working Paper – Name: URL Label: Access URL Group: URL Data: <link linkTarget="URL" linkTerm="http://arxiv.org/abs/2202.05933" linkWindow="_blank">http://arxiv.org/abs/2202.05933</link> – Name: AN Label: Accession Number Group: ID Data: edsarx.2202.05933 |
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| RecordInfo | BibRecord: BibEntity: Subjects: – SubjectFull: Computer Science - Hardware Architecture Type: general – SubjectFull: B.4.4 Type: general Titles: – TitleFull: Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ferry, Corentin – PersonEntity: Name: NameFull: Yuki, Tomofumi – PersonEntity: Name: NameFull: Derrien, Steven – PersonEntity: Name: NameFull: Rajopadhye, Sanjay IsPartOfRelationships: – BibEntity: Dates: – D: 11 M: 02 Type: published Y: 2022 |
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