Bibliographic Details
| Title: |
Mapping Spiking Neural Networks to Neuromorphic Hardware |
| Authors: |
Balaji, Adarsha, Das, Anup, Wu, Yuefeng, Huynh, Khanh, Dell'Anna, Francesco, Indiveri, Giacomo, Krichmar, Jeffrey L., Dutt, Nikil, Schaafsma, Siebren, Catthoor, Francky |
| Publication Year: |
2019 |
| Collection: |
Computer Science |
| Subject Terms: |
Computer Science - Emerging Technologies, Computer Science - Machine Learning, Computer Science - Operating Systems |
| More Details: |
Neuromorphic hardware platforms implement biological neurons and synapses to execute spiking neural networks (SNNs) in an energy-efficient manner. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition SNNs into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and inter-cluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion on the shared interconnect, improving application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a meta-heuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on the DynapSE neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and average spike latency by 21%, compared to state-of-the-art techniques.
Comment: 14 pages, 14 images, 69 references, Accepted in IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Document Type: |
Working Paper |
| Access URL: |
http://arxiv.org/abs/1909.01843 |
| Accession Number: |
edsarx.1909.01843 |
| Database: |
arXiv |
