IIZUKA, K., ITO, K., YASUDO, R., & AMANO, H. (2024). Power Optimized Design Framework for FPGA Clusters. IPSJ Transactions on System LSI Design Methodology, 17(1), 77-86. https://doi.org/10.2197/ipsjtsldm.17.77
Chicago Style (17th ed.) CitationIIZUKA, KENSUKE, KOHEI ITO, RYOTA YASUDO, and HIDEHARU AMANO. "Power Optimized Design Framework for FPGA Clusters." IPSJ Transactions on System LSI Design Methodology 17, no. 1 (2024): 77-86. https://doi.org/10.2197/ipsjtsldm.17.77.
MLA (8th ed.) CitationIIZUKA, KENSUKE, et al. "Power Optimized Design Framework for FPGA Clusters." IPSJ Transactions on System LSI Design Methodology, vol. 17, no. 1, 2024, pp. 77-86, https://doi.org/10.2197/ipsjtsldm.17.77.
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