| Title: |
A 6.7 μW Low-Noise, Compact PLL with an Input MEMS-Based Reference Oscillator Featuring a High-Resolution Dead/Blind Zone-Free PFD. |
| Authors: |
Kira, Ahmed1 (AUTHOR) ahmed.kira@mail.mcgill.ca, Elsayed, Mohannad Y.2 (AUTHOR) mohannad.elsayed@mems-vision.com, Allidina, Karim2 (AUTHOR) karim.allidina@mems-vision.com, Chodavarapu, Vamsy P.3 (AUTHOR) vchodavarapu1@udayton.edu, El-Gamal, Mourad N.1 (AUTHOR) |
| Source: |
Sensors (14248220). Dec2024, Vol. 24 Issue 24, p7963. 21p. |
| Subject Terms: |
*FREQUENCY synthesizers, *COMPLEMENTARY metal oxide semiconductors, *PHASE noise, *MICROELECTROMECHANICAL systems, *DETECTORS, *PHASE-locked loops, *VOLTAGE-controlled oscillators |
| Abstract: |
This article reports a 110.2 MHz ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications. It utilizes a 6.89 MHz MEMS-based oscillator as an input reference. An ultra-low-power, high-resolution phase-frequency detector (PFD) is utilized to achieve low-noise performance. Eliminating the reset feedback path used in conventional PFDs leads to dead/blind zone-free phase characteristics, which are crucial for low-noise applications within a wide operating frequency range. The PFD operates up to 2.5 GHz and achieves a linear resolution of 100 ps input time difference ( Δ t i n ), without the need for any additional calibration circuits. The linearity of the proposed PFD is tested over a phase difference corresponding to aa Δ t i n ranging from 100 ps to 50 ns. At a 1 V supply voltage, it shows an error of <±1.6% with a resolution of 100 ps and a frequency-normalized power consumption ( P n ) of 0.106 pW/Hz. The PLL is designed and fabricated using a TSMC 65 nm CMOS process instrument and interfaced with the MEMS-based oscillator. The system reports phase noises of −106.21 dBc/Hz and −135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. It consumes 6.709 μ W at a 1 V supply and occupies an active CMOS area of 0.1095 mm2. [ABSTRACT FROM AUTHOR] |
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