| Title: |
The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide-Based Resistive Switching Memories. |
| Authors: |
Rahaman, Sk. Ziaur1 skzia@itri.org.tw, Yu-De Lin1, Heng-Yuan Lee1, Yu-Sheng Chen1, Pang-Shiu Chen2, Wei-Su Chen1, Chien-Hua Hsu1, Kan-Hsueh Tsai1, Ming-Jinn Tsai1, Pei-Hua Wang1 |
| Source: |
Langmuir. May2017, Vol. 33 Issue 19, p4654-4665. 12p. |
| Subject Terms: |
*NONVOLATILE random-access memory, *BUFFER layers, *HAFNIUM oxide, *ELECTROMAGNETIC compatibility, *TEMPERATURE effect |
| Abstract: |
Ti/HfO x -based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfO x /TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfO x dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at ~1 μA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application, the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 h at 150 °C measurement temperature. [ABSTRACT FROM AUTHOR] |
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