Control method for memory cell
| Title: | Control method for memory cell |
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| Patent Number: | 8,817,521 |
| Publication Date: | August 26, 2014 |
| Appl. No: | 13/488937 |
| Application Filed: | June 05, 2012 |
| Abstract: | A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state. |
| Inventors: | Chen, Yu-Sheng (Taoyuan, TW); Lee, Heng-Yuan (Zhudong Township, TW); Hsu, Yen-Ya (Taipei, TW); Chen, Pang-Shiu (Hsinchu, TW); Hsu, Ching-Chih (Xinpu Township, TW); Chen, Frederick T. (Zhubei, TW) |
| Assignees: | Industrial Technology Research Institute (Hsinchu, TW) |
| Claim: | 1. A control method for at least one memory cell comprising a transistor and a resistor connected to the transistor in series between a first node and a second node, comprising: programming the memory cell in a programming mode, wherein the step of programming the memory cell comprises: providing a first controlling voltage to a gate of the transistor; providing a first setting voltage to the first node; and providing a second setting voltage to the second node; determining whether the memory cell has been successfully programmed; when the memory cell has been successfully programmed, impedance of the memory cell is in a first state, and when the memory cell has not been successfully programmed, a specific action is executed, wherein the specific action is to reset the memory cell, and the step of resetting the memory cell comprises: providing a second controlling voltage to the gate of the transistor, wherein the first controlling voltage is less than the second controlling voltage; providing a first reset voltage to the first node; and providing a second reset voltage to the second node, wherein the impedance of the memory cell is in a second state when the memory cell is successfully reset, and wherein the impedance of the memory cell in the second state is higher than the impedance of the memory cell in the first state; wherein the step of resetting the memory cell further comprises: determining whether the memory cell has been successfully reset; when the memory cell has been successfully reset, the impedance of the memory is in the first state; when the memory has not been successfully reset, at least one of the second controlling voltage, the first reset voltage and the second reset voltage is increased and the increased voltage is provided to the transistor. |
| Claim: | 2. The control method as claimed in claim 1 , wherein the first setting voltage and the second reset voltage are positive. |
| Claim: | 3. The control method as claimed in claim 2 , wherein the second setting voltage is equal to the first reset voltage. |
| Claim: | 4. The control method as claimed in claim 1 , wherein the first setting voltage is positive and the first reset voltage is negative. |
| Claim: | 5. The control method as claimed in claim 4 , wherein the second setting voltage is equal to the second reset voltage. |
| Claim: | 6. The control method as claimed in claim 1 , wherein the specific action further comprises programming the memory cell again, wherein the step of programming the memory cell again comprises: providing a third controlling voltage to the gate of the transistor; providing a third setting voltage to the first node; and providing a fourth setting voltage to the second node. |
| Claim: | 7. The control method as claimed in claim 6 , wherein the third controlling voltage is equal to the first controlling voltage and the third controlling voltage is less than the second controlling voltage. |
| Claim: | 8. The control method as claimed in claim 7 , wherein the third setting voltage is greater than the first setting voltage. |
| Claim: | 9. The control method as claimed in claim 8 , wherein the fourth setting voltage is equal to the second setting voltage. |
| Claim: | 10. The control method as claimed in claim 6 , wherein the third controlling voltage is greater than the first controlling voltage and the third controlling voltage is less than the second controlling voltage. |
| Claim: | 11. The control method as claimed in claim 10 , wherein the third setting voltage is equal to the first setting voltage and the fourth setting voltage is equal to the second setting voltage. |
| Claim: | 12. The control method as claimed in claim 6 , wherein the specific action is to execute the step of resetting the memory cell and then execute the step of programming the memory cell again. |
| Claim: | 13. The control method as claimed in claim 6 , wherein the specific action is to execute the step of programming the memory cell again and then execute the step of resetting the memory cell. |
| Claim: | 14. The control method as claimed in claim 6 , wherein the step of programming the memory cell again further comprises: providing a fourth controlling voltage to the gate of the transistor; providing a fifth setting voltage to the first node; and providing a sixth setting voltage to the second node. |
| Claim: | 15. The control method as claimed in claim 14 , wherein the first, the third, and the fourth controlling voltages are the same and the fourth controlling voltage is less than the second controlling voltage. |
| Claim: | 16. The control method as claimed in claim 15 , wherein the fifth setting voltage is greater than the third setting voltage and the third setting voltage is greater than the first setting voltage. |
| Claim: | 17. The control method as claimed in claim 16 , wherein the difference between the third and the fifth setting voltages is equal to the difference between the first and the third setting voltages. |
| Claim: | 18. The control method as claimed in claim 17 , wherein the sixth setting voltage is equal to the fourth setting voltage and the fourth setting voltage is equal to the second setting voltage. |
| Claim: | 19. The control method as claimed in claim 14 , wherein the fourth controlling voltage is greater than the third controlling voltage, the third controlling voltage is greater than the first controlling voltage, and the fourth controlling voltage is less than the second controlling voltage. |
| Claim: | 20. The control method as claimed in claim 19 , wherein the fifth setting voltage is equal to the third setting voltage, the third setting voltage is equal to the first setting voltage, the sixth setting voltage is equal to the fourth setting voltage, and the fourth setting voltage is equal to the second setting voltage. |
| Claim: | 21. The control method as claimed in claim 14 , wherein the specific action is to execute the step of resetting the memory cell and then execute the step of programming the memory cell again. |
| Claim: | 22. The control method as claimed in claim 14 , wherein the specific action is to execute the step of programming the memory cell again and then execute the step of resetting the memory cell. |
| Claim: | 23. The control method as claimed in claim 14 , further comprising: a forming mode, wherein in the forming mode: providing an initial voltage to the gate of the transistor; providing a first initial setting voltage to the first node, wherein the first initial setting voltage is greater than the fifth setting voltage; and providing a second initial setting voltage to the second node. |
| Claim: | 24. The control method as claimed in claim 1 , further comprising a forming mode, wherein in the forming mode: providing an initial voltage to the gate of the transistor; providing a first initial setting voltage to the first node; and providing a second initial setting voltage to the second node. |
| Claim: | 25. The control method as claimed in claim 24 , wherein the initial voltage is less than the first controlling voltage. |
| Claim: | 26. The control method as claimed in claim 25 , wherein the first initial setting voltage is greater than the first setting voltage. |
| Claim: | 27. The control method as claimed in claim 26 , wherein the second initial setting voltage is equals to the second setting voltage. |
| Claim: | 28. The control method as claimed in claim 24 , wherein the second controlling voltage is greater than the initial voltage. |
| Claim: | 29. The control method as claimed in claim 1 , wherein when the memory has not been successfully reset, the second controlling voltage is increased and provided to the gate of the transistor, the first reset voltage is maintained and provided to the first node, and the second reset voltage is maintained and provided to the second node. |
| Claim: | 30. The control method as claimed in claim 1 , wherein when the memory has not been successfully reset, the second controlling voltage is maintained and provided to the gate of the transistor, the first reset voltage is increased and provided to the first node, and the second reset voltage is maintained and provided to the second node. |
| Claim: | 31. The control method as claimed in claim 1 , wherein when the memory has not been successfully reset, the second controlling voltage is increased and provided to the gate of the transistor, the first reset voltage is increased and provided to the first node, and the second reset voltage is maintained and provided to the second node. |
| Current U.S. Class: | 365/148 |
| Patent References Cited: | 5748538 May 1998 Lee et al. 6707718 March 2004 Halim et al. 7006371 February 2006 Matsuoka 7289351 October 2007 Chen 7330387 February 2008 Lindstedt et al. 7342824 March 2008 Hsu 7440315 October 2008 Lung 7480174 January 2009 Lee 7483292 January 2009 Lung 7508695 March 2009 Sugita 7544968 June 2009 Toutounchi 7688635 March 2010 Tang 8223528 July 2012 Chen et al. 2004/0257864 December 2004 Tamai 2005/0141261 June 2005 Ahn 2006/0126380 June 2006 Osada et al. 2007/0186761 August 2007 Perry 2007/0228370 October 2007 Lee 2008/0062740 March 2008 Baek 2008/0130381 June 2008 Van Buskirk 2008/0165572 July 2008 Lung 2008/0266933 October 2008 Chen 2008/0291716 November 2008 Futatsuyama 2009/0003066 January 2009 Park |
| Other References: | Office Action of corresponding TW application, issued on Jul. 18, 2013. cited by applicant |
| Primary Examiner: | Luu, Pho M |
| Attorney, Agent or Firm: | Wang Law Firm, Inc. Wang, Li K. Hsu, Stephen |
| Accession Number: | edspgr.08817521 |
| Database: | USPTO Patent Grants |
| Language: | English |
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