Determining page faulting behavior of a memory operation
| Title: | Determining page faulting behavior of a memory operation |
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| Patent Number: | 8,645,758 |
| Publication Date: | February 04, 2014 |
| Appl. No: | 13/036789 |
| Application Filed: | February 28, 2011 |
| Abstract: | Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size. |
| Inventors: | Walker, Paul Michael Peter Brian Ronald (Manchester, GB) |
| Assignees: | International Business Machines Corporation (Armonk, NY, US) |
| Claim: | 1. An apparatus comprising a processor and memory to store operational components for determining page faulting behavior of at least two memory operations of a subject code block represented by an intermediate representation and a subject order list, the apparatus comprising: an inspector component for identifying, from the intermediate representation and subject order list, a first object node having a first dependency path and second object node having a second dependency path; a calculation component for calculating a numerical difference between a first addressing value and a second addressing value, the first and second addressing values respectively associated with the first and second dependency paths; and a dependency generator for ordering the subject order list in an object dependency non-page-faulting order, in response to the numerical difference being equal or less than an assigned memory page size. |
| Claim: | 2. The apparatus as in claim 1 , wherein the first and second object nodes are determined as sharing a memory page in response to the numerical difference being equal to or less than the assigned memory page size. |
| Claim: | 3. The apparatus as in claim 1 , further comprising a scheduler component for selecting a preferred execution order of the first and second dependency paths based on the subject order list. |
| Claim: | 4. The apparatus as in claim 1 , wherein the apparatus executes the first object node before the second object node in response to the first and second object nodes sharing a memory page. |
| Claim: | 5. The apparatus as in claim 1 , wherein the calculator component derives an addressing value for each of the first and second dependency paths from a common base register shared by the first and second dependency paths, and a constant offset value. |
| Claim: | 6. The apparatus as in claim 5 , wherein the numerical difference is determined based on the common base register and constant offset value. |
| Claim: | 7. The apparatus as in claim 1 , wherein each of the first and second dependency paths is associated with a plurality of object nodes and dependent nodes, and the dependency generator orders the subject order list based on the object nodes and dependent nodes. |
| Claim: | 8. The apparatus as in claim 1 , further comprises a scheduler for receiving the ordered subject order list, and means for selecting an execution order for a target code based on the non-page-faulting order. |
| Claim: | 9. A method for determining page faulting behavior of at least two memory operations of a subject code block represented by an intermediate representation and a subject order list, the method comprising: identifying, from the intermediate representation and subject order list, a first object node having a first dependency path and second object node having a second dependency path; calculating a numerical difference between a first addressing value and a second addressing value, the first and second addressing values respectively associated with the first and second dependency paths; and determining whether the calculated numerical difference is less than or equal to a memory page size assigned by an operating system; and ordering the subject order list in an object dependency non-page-faulting order, in response to the numerical difference being equal or less than an assigned memory page size. |
| Claim: | 10. The method as in claim 9 , wherein the first and second object nodes are determined as not sharing g a memory page in response to the numerical difference being more than the assigned memory page size. |
| Claim: | 11. The method as in claim 9 , further comprises electing a preferred execution order of the first and second dependency paths as identified in the subject order list. |
| Claim: | 12. The method as in claim 9 , further comprising executing a second memory operation before a first memory operation wherein the first and second memory operations are associated with a memory page. |
| Claim: | 13. The method as in claim 9 , further comprises calculating an addressing value for each of the first and second dependency paths from a common base register shared by the first and second dependency paths, and a constant offset value. |
| Claim: | 14. The method as in claim 13 , wherein the numerical difference is determined by calculating an addressing value based on the value held in the common base register and the constant offset value. |
| Claim: | 15. The method as in claim 9 , further comprising selecting an execution order for a target code based on a non-page-faulting order. |
| Claim: | 16. A computer program product for determining page faulting behavior of at least two memory operations of a subject code block represented by an intermediate representation and a subject order list, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein that executes to perform operations, the operations comprising: computer readable program code configured to identify from the intermediate representation and subject order list, a first object node having a first dependency path and second object node having a second dependency path; computer readable program code configured to calculate a numerical difference between a first addressing value and a second addressing value, the first and second addressing values respectively associated with the first and second dependency paths; and computer readable program code configured to order the subject order list in an object dependency non-page-faulting order, in response to the numerical difference being equal or less than an assigned memory page size. |
| Claim: | 17. The computer program product as in claim 16 , wherein the first and second object nodes are determined as sharing a memory page in response to the numerical difference being equal to or less than the assigned memory page size. |
| Claim: | 18. The computer program product as in claim 16 , wherein the computer program product comprises computer readable program code configured to execute the first object node before the second object node in response to the first and second object nodes sharing a memory page. |
| Claim: | 19. The computer program product as in claim 16 , wherein the computer program product comprises computer readable program code configured to derive an addressing value for each of the first and second dependency paths from a common base register shared by the first and second dependency paths, and a constant offset value. |
| Claim: | 20. The computer program product as in claim 16 , wherein the computer program product comprises computer readable program code configured to select an execution order for a target code based on the non-page-faulting order. |
| Current U.S. Class: | 714/28 |
| Patent References Cited: | 2002/0092002 July 2002 Babaian et al. 2006/0253691 November 2006 Barraclough et al. |
| Primary Examiner: | Manoskey, Joseph D |
| Attorney, Agent or Firm: | Victor, David W. Konrad, Raynes, Davda and Victor LLP |
| Accession Number: | edspgr.08645758 |
| Database: | USPTO Patent Grants |
| Language: | English |
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