Bibliographic Details
| Title: |
Mechanisms for built-in self test and repair for memory devices |
| Patent Number: |
8,605,527 |
| Publication Date: |
December 10, 2013 |
| Appl. No: |
13/291747 |
| Application Filed: |
November 08, 2011 |
| Abstract: |
Mechanisms for self-testing and self-repairing memories are efficient in testing and repairing failed memory cells. The self-test-repair mechanisms are based on self-test results of failed bit map (FBM) data of the entire memories and enable early determination of non-repairable memories to prevent and limit wasting time and resources on non-repairable memories. The self-test-repair mechanisms also involve identifying candidates for column and row repairs and allow repeated repair cycles until either the memories are deemed irreparable or are fully repaired. |
| Inventors: |
Shvydun, Volodymyr (Los Altos, CA, US); Adham, Saman M. I. (Ontario, CA) |
| Assignees: |
Taiwan Semiconductor Manufacturing Company, Ltd. (TW) |
| Claim: |
1. A method of self-testing and self-repairing a random access memory (RAM): collecting failure data of the RAM, wherein the failure data include addresses of failed cells, wherein failure data are stored in a failure bit map (FBM), wherein the RAM has a first number of redundant rows and a second number of redundant columns, and wherein the columns are divided into the second number of segments, and wherein each of the redundant columns is used for column repair of a designated segment; analyzing the failure data to determine if there are sufficient redundant rows and redundant columns to repair the failed cells in the RAM; repairing at least a portion of the failed cells by using the redundant rows and redundant columns if there are sufficient redundant rows and redundant columns to repair the failed cells; and rejecting the RAM if there are not sufficient redundant rows and redundant columns to repair the failed cells. |
| Claim: |
2. The method of claim 1 , further comprising: repeating the repairing operation until either the RAM is rejected or all of the failed cells are repaired. |
| Claim: |
3. The method of claim 1 , wherein analyzing the failure data to determine if there are sufficient redundant rows and redundant columns to repair the failed cells in the RAM includes determining if the number of rows with a segment violation is greater than the first number of redundant rows, wherein the segment violation means that there are failed cells in two or more columns in a segment for a particular row. |
| Claim: |
4. The method of claim 1 , wherein the FBM has a data structure with a third number of rows, and wherein the data structure is configured to be large enough to contain all failure data. |
| Claim: |
5. The method of claim 1 , wherein the addresses of failed cells are represented by bit addresses, and wherein locations of the failed cells are represented by codes associated with their row addresses and column addresses. |
| Claim: |
6. The method of claim 1 , wherein the collecting of the failure data of the RAM is enabled by a built-in self-test (BIST) module, and wherein the analyzing and the repairing are performed by a built-in self-repair (BISR) module, and wherein the BIST and the BISR modules are integrated with the RAM. |
| Claim: |
7. The method of claim 1 , wherein analyzing the failure data to determine if there are sufficient redundant rows and redundant columns to repair the failed cells in the RAM prevents wasting time and resources in repairing un-repairable RAM. |
| Claim: |
8. The method of claim 1 , wherein repairing at least a portion of the failed cells by using the redundant rows and redundant columns includes identifying and repairing segments with one single column with failures in the segments, and wherein the segments are repaired by redundant columns. |
| Claim: |
9. The method of claim 1 , wherein repairing at least a portion of the failed cells by using the redundant rows and redundant columns includes identifying and repairing a row or a column with a highest number of failures. |
| Claim: |
10. The method of claim 1 , wherein the RAM is selected from a group consisting of static RAM (SRAM), dynamic RAM (DRAM), and flash memory. |
| Claim: |
11. The method of claim 4 , wherein the first number is in a range from about 16 to about 50 and the second number is in a range from about 8 to about 50. |
| Claim: |
12. The method of claim 1 , wherein the method is configurable to optimize repair efficiency for the RAM with an available area for integrated circuits of the self-testing and self-repair method. |
| Claim: |
13. A method of self-testing and self-repairing a random access memory (RAM): collecting failure data of the RAM, wherein the failure data include addresses of failed cells, wherein the failure data are stored in a failure bit map (FBM), wherein the RAM has a first number of redundant rows and a second number of redundant columns, and wherein the columns are divided into the second number of segments, and wherein each of the redundant columns is used for column repair of a designated segment; analyzing the failure data to determine if there are sufficient redundant rows and redundant columns to repair the failed cells in the RAM, wherein the analyzing includes determining if the number of rows with a segment violation is greater than the first number of redundant rows, wherein the segment violation means that there are failed cells in two or more columns in a segment for a particular row; repairing at least a portion of the failed cells by using the redundant rows and redundant columns if there are sufficient redundant rows and redundant columns to repair the failed cells; rejecting the RAM if there are not sufficient redundant rows and redundant columns to repair the failed cells; and repeating the repairing operation until either the RAM is rejected or all of the failed cells are repaired. |
| Claim: |
14. A memory array with a built-in self-test (BIST) module and a built-in self-repair (BISR) module to repair a main memory of the memory array, comprising: the main memory; a first number of redundant rows for row repair of the main memory; a second number of redundant columns for column repair of the main memory, and wherein the main memory is evenly divided into the second number of segments and each redundant column is assigned for column repair in an assigned segment; the BIST module for testing the main memory; and the BISR module for repairing the main memory by using the redundant rows and redundant columns, and wherein the BISR module performs repair based on a failure bit map (FBM) generated from testing the entire main memory. |
| Claim: |
15. The memory array of claim 14 , wherein the BIST module includes an address generator, a data generator, and a test state controller, wherein a test pattern controlled by the test state controller is generated by the address generator and the data generator. |
| Claim: |
16. The memory array of claim 14 , wherein the BIST module includes a failure storage for storing failure data, a repair controller for analyzing the failure data to determine the repair method, and a repair register for registering the repaired rows and columns and the redundant columns and rows used, and wherein the failure storage includes the FBM, and wherein the FBM is updated after the repair is performed. |
| Claim: |
17. The memory array of claim 16 , wherein the failure storage further includes a failure data converter, wherein the failure data converter generates compressed failure data to be stored in a data structure for the FBM. |
| Claim: |
18. The memory of claim 14 , wherein the FBM is stored in a data structure with a third number of rows, and wherein the third number is equal to a sum of the first number and the second number, and wherein the data structure has a fourth number of columns, and wherein the fourth number is equal to the second number plus 1. |
| Claim: |
19. The memory of claim 18 , wherein the second number of columns in the data structure is used to store column indexes of failed cells, and the additional column stores row addresses of the failed cells. |
| Claim: |
20. The memory of claim 19 , wherein the addresses of failed cells are represented by bit addresses, and wherein locations of the failed cells are represented by their row addresses and column indexes, and wherein in a zero column address of a particular row represents no failure in a corresponding segment, and wherein more than one failures in a segment of a selected row is represented by a special code in the bit address. |
| Current U.S. Class: |
365/201 |
| Patent References Cited: |
6304989 October 2001 Kraus et al.
6408401 June 2002 Bhavsar et al. |
| Primary Examiner: |
Le, Vu |
| Attorney, Agent or Firm: |
Lowe Hauptman & Ham, LLP |
| Accession Number: |
edspgr.08605527 |
| Database: |
USPTO Patent Grants |
