APA (7th ed.) Citation

Inaba, S., Nagano, H., Miyano, K., Mizushima, I., Okayama, Y., Nakauchi, T., . . . Ishiuchi, H. (2004). Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology. Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, Custom integrated circuists, 225-228. https://doi.org/10.1109/CICC.2004.1358783

Chicago Style (17th ed.) Citation

Inaba, S., H. Nagano, K. Miyano, I. Mizushima, Y. Okayama, T. Nakauchi, K. Ishimaru, and H. Ishiuchi. "Low Power Logic Circuit and SRAM Cell Applications with Silicon on Depletion Layer CMOS (SODEL CMOS) Technology." Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, Custom Integrated Circuists 2004: 225-228. https://doi.org/10.1109/CICC.2004.1358783.

MLA (8th ed.) Citation

Inaba, S., et al. "Low Power Logic Circuit and SRAM Cell Applications with Silicon on Depletion Layer CMOS (SODEL CMOS) Technology." Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, Custom Integrated Circuists, 2004, pp. 225-228, https://doi.org/10.1109/CICC.2004.1358783.

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