13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

Authors: Choi, Ikjoon, Hong, Seunghwan, Kim, Kihyun, Hwang, Jeong-Sik, Woo, Seunghan, Kim, Young-Sang, Cho, Cheong-Ryong, Lee, Eun-Young, Lee, Hun-Jae, Jung, Min-Su, Jung, Hee-Yun, Hwang, Ju-Seong, Yoon, Junsub, Lim, Wonmook, Yoo, Hyeong-Jin, Lee, Won-Ki, Oh, Jung-Kyun, Lee, Dong-Su, Lee, Jong-Eun, Kim, Jun-Hyung, Kim, Young-Kwan, Park, Su-Jin, Ho, Byung-Kyu, Na, Byong-Wook, Choi, Hye-In, Lee, Chung-Ki, Lee, Soo-Jung, Shin, Hyunsung, Lee, Young-Kyu, Ryu, Jang-Woo, Shin, Sangwoong, Park, Sungchul, Lim, Daihyun, Bae, Seung-Jun, Sohn, Young-Soo, Oh, Tae-Young, Hwang, SangJoon

Source: 2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:234-236 Feb, 2024

Relation: 2024 IEEE International Solid-State Circuits Conference (ISSCC)

28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL

Authors: Kwon, Daehyun, Jeong, Heon Su, Choi, Jaemin, Kim, Wijong, Kim, Jae Woong, Yoon, Junsub, Choi, Jungmin, Lee, Sanguk, Rie, Hyunsub Norbert, Lee, Jin-il, Lee, Jongbum, Jang, Taeseong, Kim, JunHyung, Kang, Sanghee, Shin, Jungbum, Loh, Yanggyoon, Lee, Chang Yong, Woo, Junmyung, Yu, Hyeseung, Bae, Changhyun, Oh, Reum, Sohn, Young-soo, Yoo, Changsik, Lee, Jooyoung

Source: 2023 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2023 IEEE International. :27-29 Feb, 2023

Relation: 2023 IEEE International Solid-State Circuits Conference (ISSCC)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM

Authors: Hong, Seunghwan, Bae, Chang-Hyun, Sung, Yoo-Chang, Kim, Jaewoong, Yoon, Junsub, Kim, Sangwoo, Baek, Jinhyeok, Cho, Cheongryong, Shin, Useung, Kim, Sang-Kyeom, Jung, Hwan-Chul, Chang, Ho-Jun, Kim, Jang-Hoo, Hwang, Jeongsik, Kim, Hyunki, Lee, Ki-Won, Kim, Dongmin, Jeong, Han-Ki, Kim, Myung-O, Sohn, Kyomin, Ihm, Jeong-Don, Yoo, Changsik, Hwang, Sang Joon

Source: 2021 Symposium on VLSI Circuits VLSI Circuits, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Circuits

A low-power SerDes for high-speed on-chip networks

Authors: Park, Dongjun, Yoon, Junsub, Kim, Jongsun

Source: 2017 International SoC Design Conference (ISOCC) SoC Design Conference (ISOCC), 2017 International. :252-253 Nov, 2017

Relation: 2017 International SoC Design Conference (ISOCC)

A MDLL-based multi-phase clock multiplier

Authors: Yoon, Junsub, Kim, Jongsun

Source: 2016 International SoC Design Conference (ISOCC) SoC Design Conference (ISOCC), 2016 International. :247-248 Oct, 2016

Relation: 2016 International SoC Design Conference (ISOCC)

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